[SI-LIST] Re: Plane breaks - Presentation download

Eric,

I think that you can categorize return currents of
both tightly or loosely coupled diff pairs as single
ended (common mode) or differential.  The currents
that you are asking about are of the differential
variety.

The scenario that you just described is one that has
interested me for some time.  It seems unlikely to me
that the return current under A would jump on to trace
B at the split and then back under A for the remainder
of its journey.

I believe it to be far more likely for the return
current under A to encounter the reference plane split
and choose the path of least impedance.  Hopefully we
are designing differential traces containing signals
that are ideally equal and opposite.  If this is the
case, then the differential return current in the
reference plane beneath B would be equal and opposite
in orientation than the return current beneath A.  I
think that the path of least impedance for the return
current beneath A to be to simply turn around at the
split and join the current beneath B.  Even at a
spacing of 20 mils, this is much shorter length (and
inductance, thus impedance) than any other path.  This
would be difficult to see in a 2D cross section, and
if you were to render in 3D, it would be nice to be
able to see the direction of the flow.

Of course, any length mismatch or latency from Sig+ to
Sig- would cause 'error' return currents to follow the
conventional single ended return current path, which
once again will follow the path of least impedance. 
You could sum these error return currents with your
conventional SE return currents (common mode).

I have often heard it said that crossing reference
plan moats is less of a concern for differetially
routed signals than for single ended signals. 
However, I believe that this would be most applicable
to tightly matched systems.

Hope this helps,
-James


--- Eric Goodill <ericg@xxxxxxxxxxx> wrote:

> Charles,
> 
> I certainly don't consider myself any kind of
> expert--rather an 
> interested observer, but for the kind of
> weakly-coupled edge-coupled 
> diff pairs we use (e.g., 4 mil track with 8 mil
> gap), and that I 
> understand many folks use, I've seen an analysis of
> the return current 
> distributions, and the bulk of it is in the
> reference plane below each 
> trace.
> 
> Let's take traces A and B of a diff pair.  Only 20 -
> 30% of the return 
> current from A is traveling in trace B with the
> remaining 70 - 80% in 
> the reference plane underneath A.  The same is true
> of B.  Granted, 
> there is overlap of the return currents from both A
> and B in the ref 
> plane, and there's some cancellation, but there's
> still a significant 
> amount (50%?) of return current under each trace.
> 
> Or am I all wrong?
> 
> Assuming I'm right, as a diff pair crosses the plane
> split, I can't see 
> how the return current for trace A jumps from the
> plane to trace B and 
> then back down to the reference plane below A.  That
> seems unlikely to 
> me.  I would expect this return current to have to
> navigate around the 
> slot by whatever means it can which would still end
> up doing bad things 
> to your signal.
> 
> Granted, the effect would be less that you would see
> on a single-ended 
> signal due to whatever return current is in the
> other trace of the pair.
> 
> -Eric
> 
> Grasso, Charles wrote:
> > Steve/Ron - Just to calibrate myself ... Now you
> DO
> > mean a trace crossing a split orthogonally right?
> > If so I fail to see how changing the width of the
> > split makes things better except maybe in one
> condition.
> > i.e. where a diff pair cross a split. The return
> current
> > for one trace will be carried by its pair and the
> split will
> > be almost invisible.
> > 
> > The effect of crossing a split on a diff pair
> > can be seen in a presentation by Ansoft Corp
> > available for download from the RMCEMC website.
> > Go to http://www.ieee.org/rmcemc the link is
> > on the front page. You'll need to go in about 12
> > pages or so...
> > 
> > Best Regards
> > Charles Grasso
> > Senior Compliance Engineer
> > Echostar Communications Corp.
> > Tel:  303-706-5467
> > Fax: 303-799-6222
> > Cell: 303-204-2974
> > Pager/Short Message:  3032042974@xxxxxxxx
> > Email: charles.grasso@xxxxxxxxxxxx;  
> > Email Alternate: chasgrasso@xxxxxxxx
> >  
> > 
> > 
> > -----Original Message-----
> > From: steve weir [mailto:weirsp@xxxxxxxxxx] 
> > Sent: Saturday, January 22, 2005 4:19 PM
> > To: ron@xxxxxxxxxxx; Chris.Cheng@xxxxxxxxxxxx
> > Cc: Si-List
> > Subject: [SI-LIST] Re: risetime effects of plane
> breaks
> > 
> > 
> > Ron,
> > 
> > Do you really mean to imply that the cross-talk
> falls substantially if the 
> > slot gap is increased to 2H or more?  That is a
> new and very 
> > counterintuitive notion to me.  I would be very
> interested in seeing any 
> > A/B model that could demonstrate such a phenomena.
> > 
> > Regards,
> > 
> > 
> > Steve.
> > 
> > At 10:13 PM 1/21/2005 -0800, ron@xxxxxxxxxxx
> wrote:
> > 
> >>A few years ago Intel discovered that when a trace
> crosses a split it 
> >>can excite a transmission line mode into the slot
> between the panes 
> >>called "slot line" strangely enough.  If the gap
> is small
> >>it works quite well and all the traces crossing it
> become cross-talk for
> >>one another.
> >>
> >>To avoid it make the gap at least 2 or 3 times the
> thickness of the 
> >>dielectric.
> >>
> >>ADS (Agilent) has a model for slot lines with the
> other transmission 
> >>lines.
> >>
> >>Ron
> >>
> >>Chris Cheng wrote:
> >>
> >>
> >>>Scott,
> >>>Excellent summary. That was my concern on
> striplines crossing with a 
> >>>bus rather than individual signals. In a way, it
> is like wire bond 
> >>>signal leads without the ground leads mixed among
> them. The signals 
> >>>start referencing each other instead. Or you can
> see it as a 
> >>>trade-off between adding shielding layers or
> spreading the bus 
> >>>spacing (decreasing routing channels) in a high
> density/performance 
> >>>design. My own rule of thumb is space them at
> least equal or larger 
> >>>than the gap itself when crossing. That's is at
> least a 3x decrease 
> >>>in routing channels so it is quite costly and has
> to be weight 
> >>>against adding shielding layers. Sometimes its
> worth it, sometimes 
> >>>its not. As for EMI, if you dig back some
> discussion I had with 
> >>>Steve, I always prefer solid ground planes
> referencing microstrips on 
> >>>top and bottom of PCB and then stitch the edges
> with ground vias. 
> >>>Hopefully any of those excited noise on the cut
> power planes will be 
> >>>trapped inside.
> >>>
> >>>-----Original Message-----
> >>>From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> >>>Sent: Thursday, January 20, 2005 2:39 PM
> >>>Cc: Si-List
> >>>Subject: [SI-LIST] Re: risetime effects of plane
> breaks
> >>>
> >>>
> >>>When this thread started I was on vacation. 
> However, I found this 
> >>>interesting enough to resurrect some previous
> simulations I'd 
> >>>performed in CST Microwave Studio.  After much
> playing, twiddling and 
> >>>generally having fun I can say several things:
> >>>1) It's pretty easy to confirm Doug's results
> using 3D fullwave 
> >>>simulation. In fact, in about 30 minutes I can
> replicate his case and 
> >>>create a design that can be easily modified for
> many other 
> >>>possibilites.  The microstrip split plane
> crossing is a no-brainer. 
> >>>Just don't do it and expect anything approaching
> an EMI "clean" 
> >>>system.
> >>>
> >>>2) Chris and Steve ... and eventually myself,
> wanted to know more 
> >>>about the various different stripline plane
> crossing configurations, 
> >>>so I setup a simulation with a VDD island not
> unlike what might be 
> >>>found in a memory system, and performed multiple
> simulations with 
> >>>dual asymmeteric stripline crossing the plane
> twice on it's way to 
> >>>the memory module. Not surprisingly the following
> is true:
> >>>
> 
=== message truncated ===



                
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