[SI-LIST] Placement of decoupling caps (UMR paper quote.)

  • From: "Charles Grasso" <cgrassosprint1@xxxxxxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 15 Apr 2004 17:35:40 -0700

On the issue of where the place your capacitors, a statement was made that a
paper from UMR proved that placement doesn't matter and a demand for
experimental evidence was also made. As is so often the case, however, there
is a qualifier. UMR showed that capacitor placement is not critical only to
planes with a spacing of 10mils or less.

Perhaps more recent data might help.

Quote from the conclusion from a UMR paper published in the proceedings of
the Y2K EMC Symposium, Washington DC.

Paper:Experimental Evaluation of Power Bus Decoupling on a 4-layer PCB
Authors: Chen,Xu, Hubing,Drewinak, VanDoren,Dubroff
ISBN: 0-7803-5677-2

Conclusion:the measured data in this paper demonstrates power bus decoupling
in a 4-layer PCB as a function of capacitor location. mutual inductance
plays an important role in power bus decoupling above the parallel resonant
frequencies of high-frequency decoupling capacitors. When the decoupling
capacitors and the IC are in close proximity, mutual inductance between
their vias encourages the active device to draw most of the transient
switching current from the nearest decoupling capacitor when switching.
Moving the decoupling capacitor closer to the active device increases the
effectiveness of the power bus decoupling. Therefore, in 4-layer boards that
don't have closely spaced power/ground pairs, it is important to locate the
decoupling caps near the ICs. Decoupling is maximized when the capacitor via
that draws current from the farthest plane is located next to the IC power
or ground via that draws current from the farthest plane.

So placement DOES matter (apparently) for "high" impedance power planes. And
is less critical for "low" impedance power planes.

Best Regards
Charles Grasso


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