[SI-LIST] Philosophical Question about SERDES Analyses

  • From: edward kowal <kowal_edward2007@xxxxxxxxxxx>
  • To: SI LIST <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 5 Apr 2012 11:42:15 -0700

All,
I have been analyzing SERDES for some time, but have always been working for 
organizations that are designing complete, end-to-end systems.  Now I find 
myself working with a firm that only designs and controls part of the signal 
path (basically a SERDES on a daughtercard that will ultimately plug into a 
backplane).  I find myself confused as to how to proceed.  I am fortunate in 
that only two vendors make SERDES that would reside on the other (not the one I 
am designing) end of the link.  I suppose I need to make some serious 
assumptions about the backplane and any interposing cables as well.  Are 
trace/cable lengths something that every appears in a standard (I seem to 
remember that USB and DIsplayPort spec out maximum cable lengths), or is it 
purely application dependent?

Specifically, this is in the context of SAS and PCI-E if that makes any 
difference.  I have yet to review these specs in detail, and I apologize if the 
answers to my questions lay in them.
Your wisdom greatly appreciated in advance,
Ed                                                                              
  
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