[SI-LIST] Re: Parasitic capacitance of vias

Howard,

These are some very nice findings regarding via capacitance.   I have 
several comments.

1) Your statement regarding fringing capacitance being reported 100 fF 
high in other simulations, due to the lack of inclusion of the traces, 
can be misleading.  The deembedded capacitance of the via will be 
dependent upon the particular trace transisions being used.  The case 
which you seem to have simulated are top and bottom layer microstrip 
transitions.  The more usual case of stripline transitions will 
generally show a slightly higher deembedded capacitance for the via, 
since fringing still exists on the top and bottom of the via stack with 
no mutual capacitance cancelation.  

2) An additional component in the capacitance reduction is in the method 
of deembedding the trace.  Normally the trace overlaps the via, with 
trace length measurements being made to the center of the via pad.  This 
overlap for both trace insertions will be subtracted out of the total 
via capacitance during the deembedding calculations. For microstrip 
transitions, this effect can be significant as you show, since the x-y 
plane surface area of the trace will be subtracted out.  For stripline 
transitions, this effect is minimal, since only the area of the trace 
thickness, across 1/2 the circumference of the via will be subtracted out.

3) Since the via capacitance is calculated after deembedding the trace 
from the circuit, the value of the capacitance calculated will be 
dependent upon the characteristic impedance of the trace used in this 
process when deembedding microstrip traces.  (i.e. - the lower the 
impedance of the trace, the larger the effective capacitance reduction 
of the via.)

4) The capacitance of a via is generally meaningless (except as a 
relative figure of merit) without the accompanying via inductance, 
except at low frequencies where the electrical length of the via is 
small w.r.t. the edge rate or signal bandwidth being passed through the 
via.  For all design work above 2.5 Gbps, the lumped capacitance 
approximation of a via is insufficient,  a point that I am sure you will 
make in you upcoming book, "High-Speed Signal Propagation."

5) Via inductance calculations are highly dependent upon the RF signal 
return path, making an analysis of via performance at high frequencies 
very difficult, indeed.


Best regards,

scott

-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com




Dr. Howard Johnson wrote:

>Dear Ken Cantrell et. al.,
>
>[You'll find some background for this discussion in my newsletter v.5 #9
> titled "Via Capactiance"   available at www.sigcon.com -- look for
>"publications".
> This article appears near the top of the chronological listing. Inside
> the article is refers to a table of results for other interesting
>combinations
> of via capacitance. That table is located (as Mr. Cantrell points out) at
> http://www.sigcon.com/pubs/news/viacapacitance.pdf ]
>
>I've been wondering, too, about the effect of stripping pads
>from plane layers.  I'm not aware of any good approximations for
>dealing with the issue, but I did recently get my hands on some
>data that may interest you.
>
>The following analysis of via capacitance was by performed
>by Matt Hudale of Ansoft Corporation using the
>Ansoft Q3D Extractor Version 5.
>
>I provided to Matt a schedule of via configurations that were
>of interest to me.  Of course you can't do all possible
>combinations, but I tried to pick some that would clearly show the
>effect of stripping pads.
>
>In the first three tables, Matt assumed an overall board
>thickness of 0.063 in., with signal layers (and thus signal
>pads) always present on the top and bottom layers.
>In table one, the intervening space included one pair of
>reference planes, one located 5 mils below the top surface,
>and one 5 mils above the bottom surface, of the board.
>In table two, we added another pair of reference planes equally spaced
>within the board (keeping the first pair in their original
>position).
>In table three, we added yet another pair of reference planes
>interior to the layer stack, bringing the total to six
>(this includes the first two, plus four others equally spaced
>within the board).
>
>In tables 1, 2, and 3 the via drilled diameter is fixed at 12 mils.
>The first section of each table shows the results for various combinations
>of via and clearance-hole sizes, with the pads stripped on reference
>plane layers.  Note that in some cases the pad diameter exceeds the
>clearance diameter -- something that is possible only if the pads
>are stipped (this is what you might do to maintain continuity of the
>reference
>planes in very dense designs).
>The second section of each table shows the results when the pads
>are retained on the reference-plane layers in cases where it is
>geometrically possible to do so.
>
>In the first three tables Matt simulated pad diameters of
>24, 30, and 36 mils, and clearance diameters of 24, 30, and 36
>mils. Examination of the data indicated that the measured data
>formed a fairly flat surface when plotted against the pad and
>clearance diameters, so I went ahead and interpolated his data to finer
>gradations, showing interpolated results at steps of of 2 mils.
>This doesn't add any new information, it just makes it easier
>to use the table.
>
>In table four we played around with a thicker board (0.096-in.)
>and more reference planes.
>
>In all cases Matt connected short 70-ohm traces to the via. He
>measured the total capactiance of the combination of via and trace, and
>the subtracted out the capacitance of a trace of equivalent
>length (and with equivanlent fringing fields at its start and
>finish points) to arrive at a final figure for the effective
>capacitance added to the line by the presence of the via
>structure.
>
>Other simulations I have seen that look just at the capacitance
>of a via in isolation from the traces tend to report values
>of capacitance about 100 fF larger than those reported here. That's
>because a measurement made in isolation includes all the fringing
>fields from the capacitor and neglects to compute the mutual
>capacitance between the via and the trace.
>
>I hope this data is useful to you. It will appear in my upcoming
>book, "High-Speed Signal Propagation", due out from
>Prentice-Hall in early 2003.
>
>Best regards,
>Dr. Howard Johnson, Signal Consulting Inc.,
>tel +1 509-997-0505,  howiej@xxxxxxxxxx
>http:\\sigcon.com  -- High-Speed Digital Design articles, books, tools, and
>seminars
>
>---------------**begin tables**--------------------
>Copyright Howard Johnson and Signal Consulting 2002
>The following tables should be viewed with a fixed-width font.
>-------------------------------------------
>Table 5.10A-Via capacitance data for TWO reference planes
> Pad        Clearance diameter (mil)
> dia.
>(mil)
>
>        24   26   28   30   32   34   36
>
>Pads stripped
>   36   535  510  485  461  438  416  394
>   34   500  476  451  427  406  385  364
>   32   466  442  417  393  373  353  333
>   30   432  408  383  358  340  322  303
>   28   398  375  352  328  312  295  279
>   26   365  342  320  298  283  269  254
>   24   331  310  289  268  255  242  229
>
>Pads in place
>   30                                 429
>   28                            407  380
>   26                       385  358  331
>   24                  362  335  308  281
>
>NOTE(1)-HOLE DIA=12 mil, BOARD THICKNESS=63 mil, Er=4.3
>NOTE (2)-All capacitances in fF
>
>
>-------------------------------------------
>Table  5.10B-Via capacitance data for FOUR reference planes
> Pad        Clearance diameter (mil)
> dia.
>(mil)
>
>        24   26   28   30   32   34   36
>
>Pads stripped
>   36   639  599  560  521  485  449  413
>   34   603  565  527  489  454  418  383
>   32   567  530  494  457  422  388  353
>   30   531  496  460  425  391  357  323
>   28   494  462  430  399  365  332  299
>   26   456  428  401  373  340  307  275
>   24   419  395  371  347  315  283  251
>
>Pads in place
>   30                                 706
>   28                            664  613
>   26                       622  571  520
>   24                  580  529  478  427
>
>NOTE(1)- HOLE DIA=12 mil, BOARD THICKNESS=63 mil, Er=4.3
>NOTE (2)-All capacitances in fF
>
>
>
>-------------------------------------------
>Table 5.10C-Via capacitance data for SIX reference planes
> Pad        Clearance diameter (mil)
> dia.
>(mil)
>        24   26   28   30   32   34   36
>
>Pads stripped
>   36   694  649  604  560  521  482  444
>   34   654  610  566  522  485  447  410
>   32   614  571  528  484  448  412  376
>   30   575  532  489  447  412  377  342
>   28   544  503  462  422  389  355  322
>   26   513  474  435  397  365  334  302
>   24   482  445  409  372  342  312  282
>
>Pads in place
>   30                                 910
>   28                            852  780
>   26                       794  722  650
>   24                  737  665  592  520
>
>NOTE(1)- HOLE DIA=12 mil, BOARD THICKNESS=63 mil, Er=4.3
>NOTE (2)-All capacitances in fF
>
>-------------------------------------------
>Table 5.10D-Via capacitance data for 0.096-in. board
>      Drill  Pad  Clear  Ref  Via
>        ed   dia   ance   .   cap
>       hole   .,  dia.,  pla   .
>      dia.,  mil   mil   nes  (fF)
>       mil
>
>Pads stripped
>        26    38    52    4   639
>        26    38    52    6   684
>        26    38    52    8   721
>
>Pads in place
>        26    38    52    4   784
>        26    38    52    6   934
>        26    38    52    8   1081
>
>NOTE(1)- BOARD THICKNESS=96 mil, Er=4.3
>NOTE (2)-All capacitances in fF
>
>
>---------------**end tables**--------------------
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ken Cantrell
>Sent: Friday, September 13, 2002 3:15 PM
>To: degers@xxxxxxxxxxxxxxxxxxxx; chris.mcgrath@xxxxxxxx;
>si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Parasitic capacitance of vias
>
>
>
>Here it is:
>http://www.sigcon.com/pubs/news/viacapacitance.pdf
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Michael J. Degerstrom
>Sent: Friday, September 13, 2002 7:36 AM
>To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Parasitic capacitance of vias
>
>
>
>Chris,
>
>The formula provided by Johnson/Graham bounds the upper limit of the
>capacitance by assuming the via is surrounded by a coaxial shield with a
>diameter equal to the antipad diameter.  My first guess would be that the
>actual capacitance of the via is at least half the upper limit value.  Dr.
>Johnson posted a table with more accurate via capacitance estimates on his
>website several months ago, but I was not able to find it.
>
>Mike
>
>On Thursday 12 September 2002 02:28 pm, chris.mcgrath@xxxxxxxx wrote:
>  
>
>>In the Johnson/Graham text (Section 7.2), it discusses parasitic
>>capacitance being the result of several PCB parameters including the
>>diameter of the via pad and the diameter of the clearance hole in the
>>ground planes.  However, there is a caveat that states that the equation
>>"assumes there is a pad on every layer" and that if the designer omits
>>    
>>
>pads
>  
>
>>on layers not connected to traces (as we are doing), this should "slightly
>>reduce the parasitic capacitance".  Does anybody know by how much?  In my
>>case, the parasitic capacitance actually makes enough of a difference to
>>warrant asking the question.
>>
>>Thanks,
>>Chris
>>
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