[SI-LIST] Parasitic capacitance of vias


In the Johnson/Graham text (Section 7.2), it discusses parasitic capacitance
being the result of several PCB parameters including the diameter of the via
pad and the diameter of the clearance hole in the ground planes.  However,
there is a caveat that states that the equation "assumes there is a pad on
every layer" and that if the designer omits pads on layers not connected to
traces (as we are doing), this should "slightly reduce the parasitic
capacitance".  Does anybody know by how much?  In my case, the parasitic
capacitance actually makes enough of a difference to warrant asking the
question.

Thanks,
Chris

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