[SI-LIST] Re: Paper on BGA crosstalk and power system
- From: Mark Alexander <mark.alexander@xxxxxxxxxx>
- To: clifford@xxxxxxxxxxxxx
- Date: Thu, 03 Mar 2005 11:43:41 -0800
Clifford,
Thanks for providing your thoughts. Yes -- the content in the paper is
essentially the same as what's in the video... the video just has a bit
more nuance to it.
As for the question about the final simulation versus the measured
figure (with differing di/dt's) of 4.5:1... I need to take a closer look
at the data. I'm not sure that it's showing 6:1, though it could be
that on a full-device aggregated basis the disparity goes up to that
level. Either way, we'll nail that down.
With regard to hardware tests with comparable di/dt, that's a good
suggestion. I plan to code that up in the next few days. I agree that
this would be a very relevant case to look at, as in a real system,
di/dt is determined by dv/dt, which is determined (with very little
freedom) by the timing requirements of the link. One way or another,
the system designer will dial in the dv/dt he's looking for, no matter
what device he's using (assuming it's programmable, with enough degrees
of freedom in the IO settings to allow that). That makes it a good
basis to normalize to for an apples-to-apples comparison.
-mark
Clifford van Dyk wrote:
>Hi Mark
>A very interesting paper indeed. While not having seen the webcast, I
>assume that the content is more or less contained within the paper.
>While I do not see myself in the same league as other S.I. experts in
>the forum, hopefully my opinion is in some way useful. I would be
>interested to know the following:
>
>The final simulations show what looks to me like a 6 time greater
>crosstalk in the Altera package. This was done under the assumption that
>di/dt was the same for both devices. The measured results (a ratio of
>4.5:1) were made with the Altera drivers being significantly stronger
>than the Xilinx drivers. I would therefore have expected the simulated
>ratio to be less that 4.5:1, rather than the ca. 6:1 that seems to be
>indicated on figure 21. Why do you think this discrepancy exists?
>
>Also, it may have been more useful to perform the origional measurements
>with equivalent drive strengths (measured risetimes, rather than "8mA"
>vs. "8mA fast", which was by your own admission, misleading) to get a
>more apples-to-apples measurement. Do you agree?
>
>Nevertheless, very interesting! Thank you for sharing.
>
>Kind regards,
>Clifford
>
>Mark Alexander wrote:
>
>
>
>>Hey all,
>>Some of you may have already attended this, but I wanted to draw your
>>attention to a WebCast seminar and accompanying paper that was released
>>yesterday. The topic is a joint study by Xilinx and SigCon (Howard
>>Johnson) of crosstalk and power system noise in FPGA systems.
>>
>>The paper:
>>http://www.xilinx.com/products/virtex4/pdfs/BGA_Crosstalk.pdf
>>
>>The archived WebCast (might not be available until tomorrow):
>>http://www.xilinx.com/events/webcasts/tol/01feb05.htm#3
>>
>>The WebCast is a full hour with Q&A at the end; the paper /seems /long
>>but is actually pretty easy to read. I especially like Howard's
>>explanation of the crosstalk model of power system noise and why it's
>>appropriate to the large BGA scenario.
>>
>>I'd be very interested to hear feedback from people on the list --
>>factors we didn't consider, overall usefulness of the information
>>presented, ideas for future studies on the same measurement platform.
>>
>>Thanks!
>>mark
>>
>>
>>
>>
>>
>>
>>
>>
>
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