[SI-LIST] Package design considerations

 The message thread regarding bad packages that was originally prompted 
by the recent EETimes article has been intriguing to follow. It has been 
reassuring to see how many different SI experts on the list are 
cognizant that the situation described in Lee's  ongoing string of 
articles is actually a system level issue and not purely a package or 
purely a PCB problem.

Rather than delving into the many points  raised in the article and the 
many counterpoints submitted by the many  respondents  I am going to 
steer clear of those topics and speak to a slightly different area.

The following is a very broad list of issues that package designers must 
consider when designing a new package. The list is not all inclusive and 
is presented in no particular order of importance. Obviously some of the 
items are more important than others, however the relative order of 
importance can be dictated by the actual application of the part. I'm 
sure that if I devoted a little more time to it I could probably double 
the size of the list, however the point that I'm trying to illustrate is 
that package design is a multi-dimensional optimization problem. The 
package design engineer needs to perform tradeoffs and manage dozens of 
design parameters to ultimately come up with a package design that 
provides the requisite electrical performance to support the silicon to 
its full performance potential, that is manufacturable, that meets the 
target cost for the market, that is physically robust and provides 
adequate thermal performance. Also the package needs to be designed to 
allow the part to be utilized properly in the target system application. 
Conversely, the PCB that supports the packaged part needs to designed 
with many of these same issues under consideration from the PCB 
perspective. If there are shortcomings in either PCB or package designs 
the composite system may fail to perform as expected. In the list I've 
also included some modeling considerations, as modeling is important 
from a system application viewpoint. Even a 'perfect package' (whatever 
that is) will be less than 'perfect' if the supplied models are 
inadequate for the job at hand.

Ray Anderson
Senior Signal Integrity Staff Engineer
Advanced Package R&D
Xilinx Inc.



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Operating frequency
Current Consumption
Power Dissipation
Thermal Performance

Number of core power and ground balls
Distribution of core pwr/ground balls
      checkerboard pattern
      chevron pattern
      rainbow pattern
Core current return paths

Distribution of solder bumps

Number of vias
Via diameters
Anti-via size
Via grouping

Number of substrate layers
Substrate layer assignments
Substrate material

Plane perforations 
   parallel to predominant current flow
   perpendicular to predominant current flow
Plane splits

Dogbone orientation

Package decaps
   type
   number
   value
   mounting patterns

Signal routing
   microstrip
   stripline
   CPW
   impedance control
   discontinuities
   crosstalk
   return current management
   SSO management
   number of signal power and ground connections
   distribution of power and ground connections 

Package parasitic modeling
   IBIS
     per pin lumped
     per pin distributed
     RLC coupled matrix
     s-parameter
   Spice
      lumped topology
      s-parameter
   Mutual coupling
   Model extraction
   Model verification
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