[SI-LIST] Package SSN model accuracy requirements ... a bit of history

Searching the on-line IBIS Forum Summit archives 
http://www.eda.org/pub/ibis/summits/ I found the following discussion of 
package modeling, simulation, SSO and the implications of doing nothing. 
Quite an interesting list of scallywags.  Some of the observations made 
at that time are prophetic ... some are enlightening ... and yet others 
are just plain incorrect, both then and today.

Interestingly enough, these topics were dropped from IBIS Open Forum 
Summit discussions for many years afterwards.

                                    Minutes
                         Fall '93 IBIS Open Forum Summit
                           Santa Clara, CA, 11/12/93
                                   Will Hobbs

     Attendees:

     Cadence Design Systems          Zaki Rakib, Kumar
     Contec Microelectronics         Maah Sango
     Intel Corporation               Charles Anyimi, Gregg Fortner, Will Hobbs,
                                     Arpad Muranyi, Stephen Peters
     Interconnectix Incorporated     Bob Ross
     Intergraph Electronics          Walter Katz
     Logic Modeling Corporation      Randolph Harr
     MicroSim Corporation            Arthur Wong
     Performance Signal Integrity    Vivek Raghavan
     Quad Design                     Jon Powell
     Quantic Laboratories            Mike Ventham
     Siemens Nixdorf/Cadlab          Ralf Bruening
     Texas Instruments               Bob Ward
     Zeelan Technology               Hiro Moriyasu

     Agenda
     
     AM
     All                              Assemble, get acquainted, have coffee
     Will Hobbs        Intel          IC vendor view of IBIS
     Randy Harr        LMC            Die 0.9 bare die spec work with National
     Bob Ross          Interconnectix Measurement and Extraction of buffer data
     Stephen Peters    Intel          Obtaining Model Data from Simulation
     Break
     Jon Powell        Quad-Design    Slew Controlled Devices
     Arpad Muranyi     Intel          I/V/T
     Panel                            Handling Dynamic Char. of Buffers
     
     Lunch
     
     PM
     Kumar              Cadence       Simultaneous Switching Noise:  A Package
                                      Library Based System
     Vivek Raghawan     Performance   Package Parameters
                        Signal Integrity
     Break
     BIRD discussions:
     Jon Powell         Quad Design    BIRD 2
     Stephen Peters     Intel          BIRDs 1, 3, 4
 ....

 Panel discussion, chaired by Jon Powell and Arpad Muranyi: Handling
 Dynamic Characterization of Buffers

     Jon expressed dismay that some of the key drivers from the EDA industry
     were absent, notably Kellee Crisafulli of HyperLynx, and Integrity.
     For Quad, their primary interest is the device switching time (how long
     a transistor takes to turn on or off) and the delay between the turn on
     times of parallel devices.

     Stephen made the point that V/I curves vary depending on the DC point;
     Jon said that at least in Quad's case, they know how transistors turn
     on and turn off and they account for that.  If IC Vendors wanted to
     provide the more complete V/I data, you could gain 2% more accuracy,
     but at the expense of huge amounts of simulation time.

     We don't want to so complicate the gathering of data that manufacturers
     will be scared off.  We could have several levels of model so we could
     still keep it simple for those that don't want to gather the surface
     data.

     Data points could be minimized by creating a polynomial that describes
     the surface or describes the scaling factor to be applied to the V/I
     curves.

     Ground bounce simulation is the critical thing customers are after in
     wanting slew rate control information.

....

 Kumar of Cadence: Simultaneous Switching Noise, A Package Library Based
 System

     Key to modeling packaging noise is in the library: Cadence defines
     three levels in its hierarchical packaging model: I/O Cell Level (the
     circuit), Pin Level (bonding pad placement), Package Level.  Cadence
     has added a mapping file that relates an I/O model to a particular Vcc
     and ground pin.  This had been a part of the IBIS specification
     originally, but there was doubt that vendors would give out the mapping
     data, so it was dropped.

     To model Vcc, ground and signal coupling effects, the models need to
     supply Vcc information, mutual inductance and skew between switching
     times of outputs that share Vccs and grounds.

     Signal and ground mutual inductance can actually improve the ground
     bounce characteristics.  In any case, if mutual inductance has an
     effect, it is worth modeling.  The data needs to be used in the correct
     way.  If mutual inductance is included, you need to keep signals in the
     right order and make sure all are modeled; otherwise, some effects will
     not be correctly modeled.

     Cadence would like to solicit our feedback on how packaging should be
     handled; is Cadence's hierarchical approach the way we want to do it?

Vivek Raghawan of Performance Signal Integrity: Packaging.

     Vivek's presentation was a good follow-on to Kumar's discussion.  IBIS
     as it currently exists, assumes there is no coupling between pins, that
     power and ground are at fixed potentials, and it ignores the fact that
     on-die Vdd is not equal to board Vdd, etc.

     Vivek discussed the complexity of the mutual coupling, approaching a
     complex matrix of n**2 couplings (n-= number of pins).  The size of
     this matrix can be reduced by arbitrarily limiting scope of interest to
     2 neighbor pins on a DIP, or on a PGA to 8 neighbors (but which 8?  --
     depends on routing).

     Simultaneous switching of outputs (SSO) induces ground bounce that can
     result in false triggering of receiving devices, or shift the inputs of
     the IC that is switching so the inputs falsely trigger.  They also
     create timing delays at the receiving end.

     Adding in ground planes seriously complicates modeling the ground
     potential at different points on the plane (and chip) Likewise, adding
     multiple power and ground pins (as exist on most packages) is
     complicated-- you can't blindly assume they are in parallel.  Another
     complication is that package wires go through discontinuities.

     Vivek proposes an addition to IBIS with an optional [Package] keyword.
     If present, specifies .pkg file to use.  If absent, the package models
     (Rpin, etc.) in the .ibs file is used.  A .pkg file would include a
     linear sub-circuit, with valid elements of R, L, C, K.  We need a port
     naming convention.  There was a discussion between Cadence,
     Performance, Quad, Contec and TI of the use of K (applicable to Spice)
     and RLGC(?) nXn matrix representation.  Bob Ward of TI expressed the
     fear that if we use the SPICE syntax, it will send the wrong message to
     customers, that we really want to avoid SPICE syntax as much as
     possible.  Otherwise, people may be tempted to think that SPICE is
     valid at the frequencies we are looking at, which is not the case.

     Jon Powell told us of an SSO problem at one of their customers where an
     IBIS model predicted a 0.4 nS rise time, but the actual rise time of
     the part was 2 nS, due to ground bounce delays.  This underscores the
     need for package model improvements.
     

A/R Kumar: Issue a BIRD on pin mapping.

     A/R Vivek: Address how to add more complex package model including pin
     to pin coupling.

....

     Feedback, Will Hobbs and Bob Ward

     Bob Ward (Texas Instruments) and Will Hobbs (Intel) discussed devices
     that have feedback, with GTL as the front-runner of concern.  The
     discussion addressed the real problem posed by feedback, whose
     characteristics depend on the reflected wave.  We reached no conclusion
     other than that we needed to seriously address the problem quickly, and
     that it wasn't going to be easy to solve.






  

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



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