[SI-LIST] PS decoupling for QFP and similars

  • From: "Chacon Simon, Geoffrey" <geoffrey.chacon.simon@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 10 Oct 2003 09:46:06 -0600

Hi people. I'm working with an FPGA and some other logic all in leaded
packages. I was thinking about how can I provide a good decoupling, but
I found myself with some existential thoughts. The first point I came
with is that I can't decouple de PS beyond the limitations imposed by
the lead inductance. I went to some IBIS models for the QFP and the
inductance is about 10nH. Now, counting with 12 VCC pins then I may have
an average 1nH inductance. So I thought how much effort I should put in
thinking how to decouple this device if the voltage drop is already
heavily affected by this inductance. At this point, I don't know if the
device has embedded decoupling capacitors in the package, so I assume it
doesn't. The manufacturer recommends to just estimate the required
capacitance according to the power dissipated by the device, but he
never considers the voltage drop due to the inherent inductance during
the current spikes at the clock's edges.
 

For low frequencies I assume the approach is correct since the
inductance can be neglected. But what about for 150MHz frequencies and
above? Or, maybe these packages aren't designed for such high
frequencies, in which case I would have to move to BGA or smaller. And
what about with the logic in TSSOPs and alike that has similar
inductances (even lower) per pin?

 

What I would like you to tell me is how much should I worry for
decoupling such devices, and if for ~150MHz frequencies I definitely
can't use QFP and TSSOPs. Any further recommendation is welcome. Thanks.

 

geoffrey


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