[SI-LIST] Re: PLL spectrum...[follow up]

hi,
 In my earlier mail I had mentioned that
'So if input to PLL is say 300MHz and divide value in
 divider ckt is say 3 then o/p will definetly be
 100MHz'
Its should be this way 
 'So if input to PLL is say 100MHz and divide value in
 divider ckt is say 3 then o/p will definetly be
 300MHz'
 Sorry for the typo.

Regards
Partha!
--- Parthasarathy Sampath <parthsv@xxxxxxxxx> wrote:
> 
> Hi Tim,
>   Its really difficult to tell where the harmonics
> are
> generated without analysing the ckt. Here is what i
> can think of :
>  Generally PLL's are designed to lock to only one
> freq
> based on what divide by value set in the divider
> ckt.
> So if input to PLL is say 300MHz and divide value in
> divider ckt is say 3 then o/p will definetly be
> 100MHz. VCO cannot generate any other freq since its
> voltage control points to the divide-by value.
>  Moreover even if divider ckt or VCO generate
> harmonics, then PFD will not give correct phase
> shift
> and will not be able to generate correct voltage to
> VCO. Hence PLL will never lock. 
>   So my guess would be serializer generates
> harmonics.
> 
>  
>  Hope This helps
> 
> Regards
> Partha!
> --- Tim Lu <timoceous@xxxxxxxxx> wrote:
> > 
> > Hi all,
> > 
> >    I am analyzing the output spectrum of a PLL +
> > Serializer chip. Looking at the serial clock
> output
> > I
> > did see the locked output spectrum at 100Mhz. 
> > Second
> > harmonic at 50Mhz and third harmonic 25Mhz.  
> > 
> >    I do have a total of divided by 4 in the
> feedback
> > path.  In the other path the VCO output of 100Mhz
> > are
> > feed into a serializer block. Where is it also
> > divided
> > by 4 to get the low speed 25Mb/s parallel data to
> be
> > serialized to the 100Mbs.  Both the data and clock
> > comes out and the spectrum frequency I have
> > mentioned
> > above are looking at the serial clock from the
> > serializer.
> > 
> >    Here is my question, is there a way to find out
> > where the 2nd and 3rd harmonic is coming from?  Is
> > it
> > coming from the PLL feedback path or is it coming
> > from
> > the serializr divider?  I can't use the spectrum
> > analyzer to look at the  inside the chip.  I would
> > like to find out a way to test and find out where
> > the
> > 2nd and 3rd harmonic is coming from in the chip. 
> > Any
> > help is greatly  appreciated.
> > 
> > T.
> > 
> > __________________________________________________
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