[SI-LIST] Re: PI Analysis doubts (please help) - Plane pair problem

Your first problem is likely due to how you have your probes set up in 
the software.  Distributed sources and loads behave differently than 
point sources and loads.  You would be wise to get some help from your 
tool vendor or a capable consultant to advise you on how to do the 
probes properly.  If you don't you can easily get the wrong answer 
either overly pessimistic or optimistic. 

The difference between local and distributed behavior of the PDN can 
throw you off on impedance targets.  My advice is to look at each major 
IC independently. Draw imaginary lines half way between each major IC 
and model each of the islands that result with its respective IC and 
bypass caps by itself. 

A single 470uF cap is going to exhibit several nH mounted inductance.  
Guessing from your 6MHz comment you must have a target impedance over 
100mOhms.  That seems at least 4X too high for a 1.0V rail with 2.1A 
dynamic current.

Your second problem has a lot of open ground to cover.  There are lots 
of papers out there on how to select decap values.  Several are included 
in the IEC book.  Different methods have different advantages and 
drawbacks.  Fundamentally, you need to get charge where it is needed.  
To do that you have to overcome series impedance of: resistance, 
significant at low frequency, or inductance which dominates all things 
high frequency except for resonances, which it directly contributes to.  
The valid reasons to do anything that complicates a design is that it 
either attains needed performance that is not otherwise realizable, or 
it is cheaper than alternatives.  At low frequencies, multiple capacitor 
values save money and space.  At higher frequencies ... well you can 
read the papers with each of their positions.  Basically they express 
different viewpoints and priorities on the trade-offs as they relate 
mostly to resonances.  There are also different viewpoints on analysis 
of TDA or FDA.   Personally, I am a big fan of the speed and coverage 
FDA offers.  But don't be fooled by valleys in the response that only 
apply to standing waves.

At high frequencies your most viable choices to realize a working 
network are:

1) One properly selected HF capacitor value in most locations, so called 
big "V", adjusted where needed to suppress IC and PCB resonances yields 
a: simple, cheap, and robust PDN.  Requires the most homework.  
Commercial PI tools are useful if fed the right information.  The 
homework is mostly in getting the right information.  The payoff is that 
by doing all the homework you know your design will work.

2) Design a network with a distributed semi-flat impedance response 
using multiple filter poles.  Most of your ICs will not see this 
response above around 20-50MHz give or take ( depends on the IC).  It 
requires less homework dealing with resonances than the first method, ie 
less risky for novices.  But it can still have serious resonance issues. 
Altera includes a nice tool that calculates these values, and any of the 
commercial PI tools can do that as well.  

3) Design a network with a distributed semi-flat impedance response 
using one filter pole and TDK high ESR caps.  Pick an impedance target:  
Ztarget and an upper frequency limit Fmax.  The number of caps needed is 
the greater of:

Ncres = 1.2 / Ztarget ( 1uF ) OR 0.02/Ztarget ( 10uF )
Ncind = ( 600pH + Lmount ) / ( 2pi*Fmax*Ztarget )

Whichever is larger is the number of their 1uF caps you need. It is dirt 
simple, extremely robust ( all caps share AC current almost equally, a 
missing or incorrectly stuffed part causes little harm ), and when Ncres 
 > 0.5 Ncind has little exposure to IC or PCB resonances.  But it is 
VERY expensive and comparatively requires a lot of caps.  The 1uF caps 
are about $0.20 and the 10uF caps are about $0.40 in 100k quantities  
The basic conflicts of this method are that what is good for resonance 
suppression, Ncres > Ncind is bad for capacitor count.  If you have 
real-estate to spare, your name is Rockefeller, and you don't have the 
time or means to do detailed PDN design, this could be the solution for you.

With any of the methods, there are big dividends to getting the stack-up 
right for the application, choosing the right caps, and always attaching 
the caps well.  The choices made can alter the number of capacitors 
needed by 10:1 or more.  The local inductance seen by each IC drives 
what thickness laminate is required to be able to do the job at all.  
The comparative cost of laminates versus the assembled cost of different 
placed capacitor options determines which laminate and which capacitor 
options are the lowest cost.  You can find more detail in my 2009 
DesignCon paper.

Steve
Lakshmi Narayanan Sowrirajan, TLS-Chennai wrote:
> Dear All,
>
>  
>
>             There is some problem in the mailbox of min, so the
> attachment is not through and the mail was not clear in my last request.
> Sorry for the same.
>
>  
>
> Here are the details...
>
>  
>
> Problem 1:
>
>  
>
> 1          ---------------------------         => GND
>
>  
>
> 2          +++++++++++++++      => VCC_1.0V
>
>  
>
> 3          ---------------------------         => GND
>
>  
>
> With the above stack-up for the board I have taken first the 2&3 pair
> alone and simulated with cadence PI tool, where I got a normal result
> with one 470uF suppressing the noise up to 6MHz
>
>  
>
> Then I included the pair 1&2 to the simulation and proceeded with the
> multi plane simulation, were the result is some thing I don't
> understand...!!!. The reason is with one 470uF it is able to suppress
> the noise up to 10G and more. Please explain this what is the problem,
> in the stackup or in the multi plane analysis.
>
>  
>
>  
>
> Problem2:
>
>  
>
> For 1.0V, 2.1A dynamic current and 20uS response of the regulator I am
> trying to get the decap values. Can any body suggest some easy method of
> spreading the capacitor across the spectrum....? My board operating
> frequency is 600MHz so hopefully I have to suppress the noise up to
> atleast 1200 to 1800MHz
>
>  
>
> I have tried many methods as below
>
>  
>
> 1)       Method described in Black Magic book, the number of capacitor
> is coming nearly 170
>
> 2)       Method described in Power Distribution Network Design
> Methodologies chapter 5 (Barry William) there I am not able to get the
> results reflected in the cadence PI tool
>
>  
>
> Is there any other method which can give the spreading of capacitor
> across the required spectrum..?
>
>  
>
> Hopping to get a positive reply from the group
>
>  
>
>  
>
>  
>
> General Question: In SILIST can we attach files to the mails....I am not
> able to send any attachments. Please give your suggestions
>
>  
>
>  
>
> Thanks in advance
>
>  
>
> Regards,
>
> Lakshminarayanan.S
>
>  
>
>
>
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