[SI-LIST] Re: PECL to CMOS conversion
- From: Paul Levin <levinpa@xxxxxxxxxxxxx>
- To: clandrum@xxxxxxxxx
- Date: Thu, 06 Nov 2003 07:39:05 -0800
Dear Chris,
With a single-ended input, your decision point in time is determined by
when the input signal crosses some internally generated threshold. How
does your CMOS part determine this? Is it a simple voltage divider as
you used to create the dc bias voltage? Is it a fixed voltage away from
one of the rails (Vdd or GND)? Is there some internal regulation prior
to the voltage divider? How noisy is the supply to which you connected
your bias circuit? Anything that causes your bias voltage to vary with
respect to the internal reference will add jitter.
Just in case you have a noisy supply, try this: Create a 0.9 Vdc reference
using two 10 Kohm resistors in series. Now bypass the center tap to GND
with 10 uF or so of Tantalum caps. To this center tap add a 10 ohm
resistor to a 10 nF cap that goes to GND. Finally run a 75 ohm resistor
to the CMOS input which is AC-coupled to the clock signal. If the clock
input decision point has good noise rejection, this may solve most of
your excess jitter problem. If the clock input decision point has no
noise rejection, this may still reduce your problem.
This is why we are all such fans of differential inputs; we have control
over the decision point.
Good luck!
Regards,
Paul
______________________
Chris Landrum x311 wrote:
> Anyone have a good method of converting a PECL signal into a 1.8V CMOS
> signal. By "good signal", I mean one that has low jitter and is clean
> looking.
>
> Currently I have a 156MHz clock driver drving a PECL clock signal to a part
> that has a single ended clock input (1.8V CMOS). I have terminated it as
> per the following:
>
> peclclk_n is terminated with 150 Ohm res to GND.
>
> peclclk_p is AC coupled (100nF) and then terminated with a THEV
> parallel circuit to 1.8V (to set the bias). The thev term
> resistors are both 150 Ohm. This gives me a symmetrical
> swing right at 0.9V.
>
> The result is a very acceptable looking clock, but unfortunately, it appears
> to have too much jitter for the receiving device. As an example, the stated
> output jitter of the PECL buffer is
>
> JITTERosc + 2ps = ~10ps (max).
>
> I measure 25ps of cyc-cyc jitter on the input of the recieving device.
> Doesn't quite add up.
>
> Any thoughts?
>
>
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--
Paul Levin
Senior Principal Engineer
Xyratex Storage Systems
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