[SI-LIST] PECL Tree structure

Hi All,

I am having a situation in which I ve to drive the PECL clock signal to two
receiver chips. Does PECL support this sort of tree structure of clock
distribution? I assume it does not support. If it does, how to design the
transmission line termination for the two branches? How this structure will
look like?

Thanks and Regards,
Ashok.




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