[SI-LIST] Re: PDS analysis?
- From: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- To: "Istvan Novak" <istvan.novak@xxxxxxxxxxx>
- Date: Tue, 1 Apr 2008 06:56:13 -0700
Istvan,
Thank you very much for your thoughtful and detailed reply!
While the original question did not include converters specifically (assumed
low impedance external supplies or similar), your points about converter
circuits and their output capacitance is well taken. I'll mention another
frequently overlooked point is INPUT bypass capacitance for converters, often
it is under represented or poorly placed. But switching supply design is
another topic.
Your point about plane - plane coupling in a GND - PWR - PWR - GND stackup is
also well taken. The power planes will effectively reference each other to some
degree, bypass placement should consider this. At a minimum the overlap
arrangement should be well studied, and best simulated.
One key item in my post was possible operational failure modes due to
sub-optimal PDS design. It's worth noting while a circuit may apparently
function exactly as intended, it is could still essentially operationally
defective due to EMI issues. Thanks for bringing up EMI.
My original post was specifically not about return paths, and the GND - SIG -
SIG - GND stackup sets specified were to minimize this consideration. Of course
we know to always keep this issue at high priority, in terms of plane splits,
via stitching, bypass locations, etc. Thanks for bringing it up.
Also my thanks goes out to all the other responders to this thread. I continue
to enjoy the collective wisdom here.
Ivor
-----Original Message-----
From: Istvan Novak [mailto:istvan.novak@xxxxxxxxxxx]
Sent: Tuesday, April 01, 2008 6:03 AM
To: Bowden, Ivor
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] PDS analysis?
Ivor,
There have been lots of comments and discussion following your posting.
I would like to offer a few additional comments going back to your core
question: "Assuming the split power planes utilize sufficient area to
keep the point to point inductance and resistance to reasonable values,
and 0.1uF ceramic bypass caps are evenly placed at device pins, and bulk
capacitance is placed as needed, would there be reason to expect any
problems, such as plane resonance, etc?"
- as always, it depends, but there are circumstances when such a simple
network works well. If you use only one value, 0.1uF, ceramics, this
falls into the "Big-V" type, and your best bet is to use similarly a
single value of bulk capacitor. By doing so you eliminated the
potential antiresonances among bulk capacitors (because there is only
one value) and among ceramic capacitors (because there is only one
value). Staying on the board, you are left with three potential problem
areas: a) the DC source and bulk capacitor interface, b) bulk capacitor
and ceramic capacitor interface and c) ceramic capacitor to PCB
interface. For instance, if your impedance target is around 0.1 ohms
(may be good for typical rails with a few amperes current consumption),
you can use bulk capacitor(s) with 0.1 ohms ESR together with for
instance twenty to thirty 0.1uF ceramics. With typical ESR and ESL
values, this gives a nice interface between the bulk and ceramic
capacitors. Assuming a small plane puddle, this should be OK.
- the DC-source to bulk interface is an often overlooked problem area.
Too much bulk capacitance (too many uF and/or too low ESR) may drive the
converter loop into instability, or may create startup problems. Too
little bulk capacitance may result in an antiresonance peaking above
your target impedance at low frequencies. There are good simulation
aids for converter chips, but hardly anything for complete DC-DC
converter modules. If you are willing to take the time to simulate the
state-averaged converter performance with your planned PDN, ask your
converter vendors; though they do not offer these simulators publicly,
some will make it available for you if you ask.
- the ceramic capacitor and plane interface has a few potential issues:
a) antiresonance between the static plane capacitance and inductances of
bypass capacitors, b) modal resonances of planes and c) too much
inductance presented to active devices. These risk areas are
inter-related. For instance, using thick laminates makes solve a)
easier but solve c) harder and vice versa. Regarding b), your best bet
is to make component placement such that your plane-shape size is minimized.
One additional comment about the stackup: having paralleled power stack
in the middle between ground planes is good for isolating power splits
from high-speed traces (no issues with traces crossing splits), but the
vertical coupling between the plane shapes above each other is very
strong at high frequencies: you need to make sure that you dont allow
vertical overlap between very noisy and very sensitive (supposedly
low-noise) rails.
The above are considerations of the primary PDN function, delivering
clean power to the chips. As Chris always points out, the return-path
function always needs to be looked even if on your board traces do not
reference power planes.. Our EMI-prevention goals are usually covered
in the regular PDN design process by suppressing plane resonances.
Regards,
Istvan Novak
SUN Microsystems
Bowden, Ivor wrote:
> Hi SI Experts,
>
> Say you have a typical PCB with modern technology mix of CPU, DSP, DDR, GIGE,
> PCIE, etc. Say it is a multi-layer stackup in the form of GND-SIG-SIG-GND
> sets, with the power distribution centered in the stackup as solid ground
> plane - split power plane - split power plane - solid ground plane, using 1oz
> copper and 3.5 mil dielectric. Assuming the split power planes utilize
> sufficient area to keep the point to point inductance and resistance to
> reasonable values, and 0.1uF ceramic bypass caps are evenly placed at device
> pins, and bulk capacitance is placed as needed, would there be reason to
> expect any problems, such as plane resonance, etc? If so, what would be the
> observable real world manifestations, in terms of circuit performance and
> power pins scope waveforms? Would there be significant advantage to analyzing
> this PDS, or should following this "industry standard practice" for PCB PDS
> be sufficient to expect robust behavior?
>
> Thanks,
>
> Ivor Bowden
> Senior Hardware Engineer
> Curtiss-Wright Controls Embedded Computing
> 10201 Wateridge Circle
> Suite 300
> San Diego, CA 92121
> 858-452-0020 x 4405
> ibowden@xxxxxxxxxxxxxxxxx
>
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