[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance?
- From: "H. Selfridge" <harrys@xxxxxxxxxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sat, 22 Feb 2003 10:37:56 -0800
The question was - has anyone tried plugged vias.
We have used plugged vias in ultra-fine-pitch BGA pads. The process is
manpower intensive, hence expensive. After fab, and before Au/Ni plating,
conductive silver resin is forced into the via holes. Once set, the resin
is burnished, then the board is plated.
This process has served us well; however, as mentioned above, it is
expensive. It also would not be suitable for most mil-spec assemblies. I
know of no studies concerning reliability of the pad. Intuition suggests
that the dissimilar materials bonded together will not do well in the long
haul where stress and temperature cycling occurs. We used it to quickly
solve a problem in a limited, disposable, application.
There is another expensive process that can be used that is more
stable. Laser drilling to controlled depth can be used to produce micro
vias in pads. The laser is used to create a hole about 4mils diameter from
the surface pad down one or two layers to a buried pad. The resulting hole
is then copper plated to create a blind via connecting the surface pad and
the buried pad. When the board is surface plated, the microvia fills in
and becomes a barely perceptible dimple in the surface pad.
Both of the above are 'exotic' techniques not suited for mass production
(unless you plan to charge a hefty price for the finished goods).
At 06:46 PM 2/21/03 -0800, you wrote:
>I haven't done it, but my understanding is that some fab houses can plug
>the vias then plate over them. The mounting pad then has the via hidden
>underneath it. This would certainly give the lowest inductance.
>
>see:
>http://www.protoengineering.com/pdf/viaplug.pdf
>
>
>http://www.methode.com/mdc/mdc5.htm
>
>Has anyone tried this?
>
> -tom
snip
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