[SI-LIST] Re: PDS Capacitor Mounting Details for Lowest Inductance?

Steve,

I discussed the same issue with our PCB fab house and PCB
assembly/manufacturing engineers.  PCB Fab house does not have any objection
for via in pad but the assembly house will not like it for the reason that
during assembly, the solder paste will be sucked in to the via in the pad
and the decoupling cap may not have sufficient solder. This causes quality
and reliability issues, short/long term. Alternative is to fill the vias and
then assemble the components, but this will add one additional step in
manufacturing and so increased assembly cost(saving even pennies is
important in this economy!).  This issue is more severe with smaller
components like 0603 and smaller.  I suppose you will be using smaller
components for decoupling caps as they will have lesser lead inductance.
The via (small like 10 mil)in pad is not a serious problem with 0805
components or bigger as those components will have more solder paste.

You can use via next to pad and this via when covered with solder mask will
not cause above assembly problem and is a compromise(I am using it!).

Thermal relief is given for vias of components so that heat is not conducted
to the plane, thus causing solderability issues to the component.  But vias
for connection between planes and decoupling vias do not have this problem.

The preferred stack up depends on the impedance you want to achieve on the
signals.  In 4 layer case, it will be difficult to get good plane
capacitance as you have to use a thick core for getting the PCB thickness of
0.062".  You may prefer to optimize the stack up for impedance than for
getting better plane capacitance, and leave the decoupling to the discrete
capacitors or capacitor arrays.  Broadband decoupling covering the frequency
range of interest is important.   

Hope this helps,
Prasad


-----Original Message-----
From: Steve Lund [mailto:slund@xxxxxxxxxx]
Sent: Friday, February 21, 2003 2:10 PM
To: Signal Integrity Listserv (E-mail)
Subject: [SI-LIST] PDS Capacitor Mounting Details for Lowest Inductance?



Si Gurus,

This subject has been discussed at length on this list and I agree on the
need to minimize the mounted capacitor inductance but have a few questions
regarding the actual application. Befor I get started please realize that I
am a circuit designer with limited knowledge about actual PCB design. So far
most of our designs fit on standard 4 layer PCBs (signals on the outside and
power and ground in the middle).

1. Is it possible to do via-in-pad (prefered) or via-next-to-pad without
incurring extra cost or manufacturability penalties? At one time I believe
that one of our vendors didn't like this approach for a reason that I don't
remember. What is the current thinking on this approach among PCB
manufacturers? 

2. What about thermal reliefs for the connections to the internal power and
ground layers? These originated for solderability reasons on through-hole
boards. Are they still required on SMT mounted bypass caps? I know that
these are not wanted due to the increase in mounting inductance that they
cause. Is it possible to get rid of these without incurring
manufacturability problems? If not is there a recommended geometry?

3. Does anyone have a prefered stack up for 4 layer .062" boards? I would
like to have as much plane capacitance as possible. For high plane
capacitance you need close pwr-gnd plane spacing but this then leads to
large spacing over planes for the signal layers. Added to this is the fact
that needed dielectric layers are only available in certain standard sizes.
Does anyone have any recommendation for a compromise stack-up that would
work good for these conditions?

If would also appreciate any links that you could give me where I could
learn more about the practical aspects of implementing this PDS strategy in
a PCB. It would also make it easier to send known good information to our
PCB designer.


Thanks for your thoughts,

Steve

Steve Lund
Sr. Design Engineer
OPW Fuel Management Systems
114-300 Mackenan Dr.
Cary, NC 27511
(919)460-6000 x2133
(919)460-7595 FAX
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: