[SI-LIST] Re: PCIe routing
- From: Istvan Novak <istvan.novak@xxxxxxx>
- To: Girish Gopi <girish.gopi@xxxxxxxxxxxxxxxxxx>
- Date: Sun, 12 Jul 2009 09:29:53 -0400
Girish,
From your description it looks to me that you deal with a board with
sequential lamination, and two sub-composite pieces, maybe layer 1-10
and layers 11-20 are built first before gluing them together. In any
event, the fact that your blind vias penetrate several layers will
result in a stub-notch frequency less than what you would expect just
based on the time-of-flight along the length of the via in the same
dielectric. If you want to squeeze the most out of your design, a 3D
field solver simulations looks necessary.
Regards,
Istvan Novak
SUN Microsystems
Jory McKinley wrote:
> Hello Grish,
> Well lets see, the electrical length of the blind via you described is
> roughly 10ps. For PCIe gen 2 the minimum rise/fall time is 30ps so these
> vias could create impedance mismatches for your channel. I would try and
> match as close as possible to your trace impedance with sufficient ground via
> returns. If you are able try and model these vias in the channel with a 3D
> simulator.
> Regards,
> -Jory
>
>
>
>
>
> ________________________________
> From: Girish Gopi <girish.gopi@xxxxxxxxxxxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Saturday, July 11, 2009 7:32:10 AM
> Subject: [SI-LIST] PCIe routing
>
> Hi all,
> I am having the 20 layer pcb with 3MM thickness , using blind vias from 1 to
> 10 and 11 to 20 layers.Where 2nd layer using for PCIe(5GB/S) routing , can I
> know that the via used for PCIe routing from layer 2 to 10 , will it be act
> as a stub ?Is there any issues?
>
> Thanks in advance
> Girish
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