[SI-LIST] Re: PCIe Impedance

Nikhil,

Within the range, lower Zo means wider traces which has smaller loss if the 
design requires longer trace length. But that would also translate to a bit 
more PCB space for the design. On the other hand, with the fixed driver 
impedance, lower Zo may lead to more pounced Txline kinks on the rising/falling 
edges, and requires stronger driver to compensate/mitigate the effect. 

Vice versa for choosing a design with higher Zo.

If your design involves a connector to a daughter card, you will also need look 
at impact from the inductive pin of the connector. Choosing trace with proposer 
Zo will mitigate the effect of connector.

Hope this helps. Some quick pre-layout simulation can help you gain insight of 
the trade-offs.


Catherine Xu
__________________________________
Lead HW Design Engineer, Ph.D
HP ICS  CHIL - San Diego
__________________________________ 


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of npatel@xxxxxxxxxx
Sent: Wednesday, March 17, 2010 2:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] PCIe Impedance

Hi all,
 

PCIe base spec specifies differential impedance to be in the range of
80-120 (100ohms nominal). PCIe Electromechanical spec calls out 68 to
105 (~86ohms). 

 

Does anyone know which is correct? I have heard the general practice is
to use 85ohms.

 

Thanks,

Nikhil

 


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