[SI-LIST] PCIe DCD / Jitter simulation


I'm just looking in PCI express gen2 simulations, but do not fully
understand the Spec regarding DCD and Jitter (low and high frequency)
for worst case simulations.

There is mentioned, that the simulation should be done with 0.1 DCD.
Additionally there are 78ps Dj and 28ps for slewing the eye.

0.15UI is the max. High Frequency TX jitter. From this 30ps (0.15UI) 
one should include 0.1UI (20ps) as DCD in the simulation.
==> What is the Jitter distribution, that should be assumed here?
I guess a fixed 0.1UI DCD is not correct. Personally I would use +-
0.05UI with some gaussian distribution, but I'm not sure if this is the
intension there.
This would reduce the eye size, but still results in a nice symmetric eye.
So in my understanding this is not really a Duty cylce distortion with
e.g. each even bit short and each odd bit long, but high frequency
jitter e. g. introduced by SSO noise and package x-talk.
==> Is my understanding correct ?

Additionally there is a value of 78ps Dj mentioned. not sure if I need
to add this in simulation or data evaluation, or if this is accounted
for by the DCD already.
==> My understanding is, that this is the max value of the sum of the
0.1DCD + the Jitter introduced by the channel.
Is this correct, or do I need to add this DJ in addition (in simulation
or data evaluation)?
I can evaluate this, but if I place a Receiver eye mask it should be
enough not to violate the mask, correct ?

Finally there is there is the jitter that I need to add in the
dataevaluation by slewing the eye (e. g.  28.9ps for common clock
==> is it OK to expand the eye mask by this number (+-15ps from the
center) ?

So far i have not seen any documents that describe it in a way that I
would understand it (guess I'm just to stupid).  Maybe somebody can
enlighten me here, or point me to some description.

Thanks and regards


EKH - EyeKnowHow
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