[SI-LIST] Re: PCI-X 1.0a simulation

Chris
I'm in agreement with you. PCI-X is a reflected wave bus, which makes it 
extremely sensitive to bus length, loading, SSO and other package 
effects.  PCI-X busses that I have seen were designed into low cost 
packages that had extreme issues with power delivery and signal 
crosstalk.  In some, where the drivers had fast edges and low output 
impedance, reflected reverse crosstalk generated in the package 
dominated performance.  In fact, in some cases it was not possible to 
design PCB traces that had worse crosstalk than the package.  In other 
cases, "PCI-X receivers" did not meet the voltage tolerance required by 
the specification, causing us to use vast numbers of series attenuators 
to keep overshoot from blowing up the receivers.  In yet others, FET 
switch packages used for hot-swaping, generated more signal-to-signal 
crosstalk than any other component or trace.

I'm generally not comfortable with running PCI-X at bus rates above 66 
MHz, without some significant spice modeling of drivers, receivers and 
packages.  Many 100 MHz busses that I've looked at are marginal, with 
133 MHz being a pipedream (http://en.wikipedia.org/wiki/Pipe_dream), 
except for short point-to-point interconnect.

regards,

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Mcgrath, Christopher wrote:

>Having done a significant amount of PCI-X 1.0 simulations in my last
>life, I concur with all of the comments so far.  There is a tremendous
>difference between driver models for various ASICs even if they are all
>consistent with the PCI-X specification.  I also found that not having a
>package model (or at least an approximation to start out with) can
>severely skew the results to the point that simulating without them is
>pretty much a waste of time.
>
>We had to "make do" with an IBIS model from a vendor and they took a
>while to get us a version with the package data incorporated into it, so
>we did some analysis without it.  When we finally got the full model, we
>saw that we had less margin on timing but significantly less transient
>overshoot/undershoot. =20
>
>-Chris
>
>
>  
>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>>    
>>
>[mailto:si-list-bounce@xxxxxxxxxxxxx] On
>  
>
>>Behalf Of Aubrey_Sparkman@xxxxxxxx
>>Sent: Tuesday, December 27, 2005 4:02 PM
>>To: weirsi@xxxxxxxxxx; naren.thesia@xxxxxxxxx
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: PCI-X 1.0a simulation
>>
>>Naren,
>>Please take another look at the specs.  There are several important
>>differences between the PCI spec and the PCI-X spec so I would strongly
>>discourage using a generic PCI model for a PCI-X driver.
>>
>>You can make a buffer model that covers the max and min conditions from
>>the spec.  Can you get the package models for your ASIC to use with the
>>buffer model?
>>
>>Most GOOD system houses have faced conditions like this.  You start
>>    
>>
>with
>  
>
>>the appropriate (PCI VS PCI-X) "spec based" model until your ASIC
>>supplier gets their silicon finished and their model working and
>>correlated.  Then you continue to use your "spec based" models to test
>>for the range of things that can be plugged into your slots.
>>
>>Good luck,
>>Aubrey Sparkman
>>Enterprise Engineering Signal Integrity Team
>>Dell, Inc.
>>Aubrey_Sparkman@xxxxxxxx
>>(512) 723-3592
>>
>>-----Original Message-----
>>From: si-list-bounce@xxxxxxxxxxxxx
>>    
>>
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
>  
>
>>On Behalf Of steve weir
>>Sent: Tuesday, December 27, 2005 6:53 AM
>>To: Naren Thesia
>>Cc: si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: PCI-X 1.0a simulation
>>
>>Naren,  I am sorry, but I don't see anything here to change my opinion.
>>Steve
>>At 04:54 PM 12/27/2005 +0530, Naren Thesia wrote:
>>    
>>
>>>But my ASIC is in development stage.
>>>For IBIS mainly two things
>>>   * Pin & package parasitics
>>>   * VI characteristics of buffer.
>>>I have package/pin parasitics of ASIC(Driver).
>>>Now I want to take VI characteristics from other device model.
>>>The reason behind I am assuming is that PCI output will be standard as
>>>PCI specifications.
>>>
>>>Please let me know about your opinion....
>>>
>>>
>>>
>>>
>>>On 12/27/05, steve weir <<mailto:weirsi@xxxxxxxxxx>weirsi@xxxxxxxxxx>
>>>      
>>>
>>wrote:
>>    
>>
>>>I wouldn't do that.  Get the driver model.
>>>
>>>Steve.
>>>At 04:22 PM 12/27/2005 +0530, Naren Thesia wrote:
>>>      
>>>
>>>>Hi all,
>>>>
>>>>In my circuit there are two devices PCI-X 1.0a driver and receiver.
>>>>I have IBIS model for receiver.
>>>>I don't have IBIS model for driver.
>>>>
>>>>Can I use any generic PCI model for my driver?
>>>>Anyone has faced condition like this?
>>>>
>>>>Thanks in Advance.....
>>>>
>>>>--
>>>>Regards
>>>>Naren
>>>>
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