[SI-LIST] Re: PCI and PCI-X bus noise

  • From: Christopher Jakubiec <Christopher.Jakubiec@xxxxxxx>
  • To: scott@xxxxxxxxxxxxx
  • Date: Thu, 16 Oct 2003 10:10:35 -0700

Scott,

Regarding your second area of concern that you stated "FET switch crosstalk", 
exactly what parasitic capacitance in the substrate are you referring to?  I am 
aware of gate to substrate capacitance, and source/drain junction capacitance, 
what are you referring to?

Thank You,

Chris Jakubiec
Sun Microsystems



Scott McMorrow wrote:
> 
> All,
> 
>  From previous work I performed on the PCI-X bus, the noise
> specification was rather ill-defined.  Package-level noise was never
> even included or anticipated in the budgets.  This is a bad thing.
> 
> There are two areas that are of most concern for PCI-X.
> 
> 1) Package crosstalk.  Since the bus is not terminated, reflected
> reverse crosstalk can become quite significant and one of the most
> dominant factors in noise margining.  You'll need to perform
> measurements designed to isolate SSO noise from package crosstalk.  This
> can be done by knowing the layout of the package and selecting a set of
> adjacent signals to switch in three ways.
>     a) switch only the center line as a base line measurement
>     b) switch all signals simultaneously in the same direction for even
> mode crosstalk
>     c) switch all neigbors to the center signal in the opposite
> direction as the center for even mode crosstalk.
> With these sets of measurements (since the remainder of the drivers on
> the bus are quiescent) you will see package crosstalk quite clearly.
> 
> 2) FET switch crosstalk.  If you are using a hot-swap design with FET
> switches, be very very careful.  FET switches have significant crosstalk
> between channels that is caused by parasitic capacitance in the
> substrate.  Packages for these devices usually have large ground
> inductance which does not effectively ground out the substrate
> parasitics. As a results, you literally see what amounts to simultaneous
> switching crosstalk between the channels.  This can be quite high, and
> in some systems will be the dominant noise.  And, since the switch
> placement varies from design to design, and the bus is not terminated,
> this noise can reflect all over the place and be quite problematic
> 
> regards,
> 
> scott
> 
> Grist, Robert wrote:
> 
> >Also make sure you are not viewing signal conditions during tri-state
> >conditions. Noise during this time is not important.
> >
> >
> >-----Original Message-----
> >From: Gregory R Edlund [mailto:gedlund@xxxxxxxxxx]
> >Sent: Wednesday, October 15, 2003 10:03 AM
> >To: swldstn@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> >Subject: [SI-LIST] Re: PCI and PCI-X bus noise
> >
> >
> >Steve,
> >
> >I applaud your efforts in making quiet line measurements on PCI/X.  This
> >is
> >an important part of the SI verification process but a difficult one
> >because you need to have control over bus patterns, be able to trigger
> >on
> >the pattern of interest, and verify the switching state of the
> >neighboring
> >lines.  In my opinion, it's well worth the effort to isolate crosstalk
> >and
> >SSN from reflections as much as possible.  Do this by switching only one
> >bit on the bus (reflection), all bits (SSN), and a small number of
> >aggressors around your quiet line (crosstalk).
> >
> >The other thing that you can do to determine whether or not you're in
> >trouble is to attempt to place the noise events in time relative to the
> >input clock at the receiver chip.  You will need to scope both the quiet
> >line and the clock as close to the die pad as possible.  Construct a
> >setup
> >and hold window around the clock using what you know about clock skew
> >and
> >the PCI/X timing specs.  Do your noise events fall within this window?
> >What if your drive chip speeds up or slows down?
> >
> >I see from my (old) copy of the PCI-X spec that you have 825 mV of noise
> >margin to work with on the low level, assuming Vcc =3D 3.3 V.  They =
> >break
> >out
> >reflections, crosstalk, and input reference offset but not SSN.  I guess
> >I
> >would have broken out crosstalk, SSN, and input reference offset and
> >left
> >reflections as part of propagation delay.  At any rate, you'll need to
> >look
> >at your 1.2 V and determine how much of it is crosstalk and SSN that can
> >occur inside the setup and hold window.
> >
> >Greg Edlund
> >Senior Engineer
> >Signal Integrity
> >IBM Engineering and Technology Services
> >3605 Hwy. 52 N, Dept. HDC
> >Rochester, MN 55901
> >gedlund@xxxxxxxxxx
> >
> >
> >
> >Msg: #11 in digest
> >Date: Tue, 14 Oct 2003 13:49:36 -0400
> >From: swldstn@xxxxxxxxxxxx
> >Subject: [SI-LIST] PCI and PCI-X bus noise
> >
> >To all,
> >
> >In doing some targeted simultaneous switching noise
> >data patterns on a PCI and PCI-X bus we see total
> >noise of between 0.5 to 1.2 volts depending on bus
> >configurations. This voltage is the sum of ground bounce
> >ringback, reflections, etc when looking at a quiet
> >high or low pin. At this time its hard to separate
> >out the source of the noise. The device under test is
> >part we have designed.
> >
> >Is anyone willing to share their experience or point
> >me to some published information on PCI and PCI/X?
> >
> >Any help is appreciated. Thanks in advance.
> >
> >Steve Waldstein
> >swldstn@xxxxxxxxxxxx
> >
> >
> >
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> --
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 239-5536
> http://www.teraspeed.com
> 
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