[SI-LIST] Re: PCI IO buffer problem?
- From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
- To: "todd t" <tamast@xxxxxxxxx>, "yinhongcheng" <yinhc@xxxxxxxxxx>
- Date: Thu, 4 Sep 2008 08:44:33 -0400
One thing I've noticed with new CMOS drivers is that the slew rate is
usually much higher than the PCI spec allows. I measured an IBIS model
for a newer processor with a PCI interface that was 8x faster than the
fastest allowable PCI slew rate. (I told them about this, they responded
that they never claimed to be PCI compliant.)
These faster edges will eat away at timing and noise margins.
The other concern is the driver should be a relatively weak. (this is
also defined in the spec.)
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of todd t
Sent: Thursday, September 04, 2008 6:24 AM
To: yinhongcheng
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: PCI IO buffer problem?
most likely the PCI specific I/O would include additional voltage
clamps. there may be other differentiating items, but that would be
the most significant.
ciao,
-todd t
On Sep 4, 2008, at 4:36 AM, yinhongcheng <yinhc@xxxxxxxxxx> wrote:
> Hi, All,
> Some vendor or foundry provides special PCI(33Mhz or 66Mhz) IO
> buffer in their IO buffer
> library during ASIC design,but some not.
>
> So I want to know what is the difference between common CMOS
> logic IO and special PCI IO, if
> we can use commom IO buffer replace special PCI buffer during ASIC
> design?if do so, what factor
> (such as Hot-plugging and so on) should be take into account? thanks!
>
>
>
>
> Best Regards
> HongchengYin
>
>
>
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