[SI-LIST] Re: PCI Bus Routing

Ira:
With appropriate respect to the prior three respondents, I must offer the 
following caution. Since each of the PCI chips are expected to be a driver as 
well as a receiver, a worst-case simulation (per PCI Specification allowable 
limits) of daisy-chained connections will likely indicate an unacceptable 
settling 
condition (caused by reflections) versus time for maximum driver strengths 
(i.e., lowest allowed source impedance and maximum slew rate). The use of short 
stubs WITH a series damping resistor at each chip will alleviate this 
potential error condition (similar to the recommended PCI daughter card design 
recommendations).

As noted by others, as a minimum you should generate models and perform a 
simulation. Be sure to use the strongest driver model data provided by the 
respective chip vendor, or preferably use the PCI allowable limits which will 
allow 
second source part substitutions if needed downstream. The simulation result 
may allow deletion of the series damping resistor if the driver is weak enough. 
Zero-ohm resistors may be used if the layout is done in parallel with your 
analysis. Also, check to verify any reflections at the individual receivers do 
not exceed allowable votage-time limits. This condition may arise if a clamp 
circuit to the positive rail is not included inside the chip. My recent 
experience (last three months) has shown that a high percentage of chip vendors 
do NOT 
meet the PCI Specification limits on drivers, even though they include "PCI" 
in the name of the chip. Nor do all PCI chips include positive rail clamps. 
The receiver performance is barely affected by the presence or absence of the 
series damping resistor.

Note also that the use of stubs with damping resistors will likely reduce the 
total length of the bus relative to the daisy-chain approach.

Good Engineering to you,

Mike

Michael L. Conn
Owner/Principal Consultant
Mikon Consulting
Cell: (408)821-9843

                   *** Serving Your Needs with Technical Excellence ***


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