[SI-LIST] Re: PCI Bus Routing

This might be usefull ..

In practical terms, routing all the tracks in parallel
- is easy to hand guide / route
- generates shortest possible tracks (prove me wrong!)
- generates a pattern of reflections similar to a backplane (staggered in
time so there is no late, large reflection anywhere)
- minimises vias, board area etc
- contains signals that are 'switching together' in one area

If the devices are actually a bunch of adjacent connectors this is pretty
obvious.

If the devices are a mix of chips, than local fan out at each chip to a
'connectivity layer' works well.
The connectivity layer has tracks running in parallel like a backplane.
Checking the direction that AD00-31 increments around the chips may lead to
some order in rotational placement of chips, and track order.
Connect up the farthest devices to create the 'backplane'.
Then add the midway parts, fanning out to the innerlayer tracks.

If you wanted to get really tricky, then you could add 10 ohms series
resistors at each device and set the inner layer same as cPCI. this would
allow the PCI clock to be as unlimited by connectivity as possible.


Jon Keeble.

----- Original Message ----- 
From: "David Fogel" <dfogel@xxxxxxxxxxxxxxx>
To: <ira@xxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
Sent: Friday, May 30, 2003 4:19 AM
Subject: [SI-LIST] Re: PCI Bus Routing


> Daisy chain is the better routing. You will have less reflections relative
> to stub routing which will help in the signal settling to its desired
level
> in the allotted time window.
> David
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Ira Kravitz
> Sent: Thursday, May 29, 2003 4:48 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] PCI Bus Routing
>
>
> Hi,
> Should a PCI Bus (32 /33M) going to 9 devices be routed in a daisy chain
> fashion (will be about 16 inches long) or as a bus with stubs hanging off
> it.
> Thanks
> Ira Kravitz
>
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