[SI-LIST] PCB layout: How to choose allowable crosstalk?

I need to come up with some design rules for PCB layout, and I'm a
little unsure on how to proceed with regards to choosing the allowable
amount of crosstalk.  The data busses in question is 10 bits; it's the
10B encoded data to and from an HP SerDes, HDMP-2630B.  This part uses
SSTL-2 signaling, but -- according the data sheet -- there's only 30mV
of noise margin in the "worst case."  (Voh_min is spec'd at Vreft+.38
and Vih_min is spec'd at Vreft+.35; I'm assuming the real receiving
device has comparable thresholds.)  If I choose my design rules to allow
even a relatively large fraction of that 30mV to be crosstalk, I'm going
to end up with some pretty widely spaced traces!

So... how does one typically proceed in choosing allowable crosstalk?
Just talking some large percentage of the signaling standard's noise
margin?  50%?  75%?  And using the noise margin in the... worst case?
Nominal case?  (Although the HP data sheet, at least, doesn't provide
nominal case noise margins.)  Any insight here would be greatly
appreciated.

Thank you, 
---Joel Kolstad 



------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: