[SI-LIST] Re: PCB layer stackup
- From: Ed Linke <ed@xxxxxxx>
- To: symon_brewer@xxxxxxxxxxx
- Date: Tue, 09 Jan 2007 09:24:48 -0500
Hi Stuart,
Your stackup #2 is the correct choice to prevent warpage especially
if this is a substrate for a device package with buildup outer layers.
In stackup #1 with build up technology, layers #4 and 5 are the core
layers. With routing on 1 layer, it stress relieves that layer cousing
possible warpage. In Stackup #2 layers 4 and 5 are balanced and cancel
one another.
The outer layers with buildup technology are of less concern.
Ed. L.
Symon wrote:
>Hi Stuart,
>To the best of my knowledge, and IME, I think you're mistaken. As long as
>the cores and prepregs etc. are symetrical there won't be a warpage problem.
>The copper planes per se don't matter. The designer can even use copper
>balancing if they're paranoid!
>HTH, Syms.
>
>----- Original Message -----
>From: "Stuart Brorson" <sdb@xxxxxxxxxx>
>
>
>
>
>>Forgetting about any minor SI advantages/disadvantages, stackup 1 has
>>the major disadvantage that the plane layers are unbalanced, which can
>>lead to board warpage. That is, the planes will strain the top
>>layers of stackup 1 more than the non-plane bottom layers, which can
>>lead to bent, warped boards. The problem would become acute over wide
>>temperature ranges. I'd stick with stackup 2.
>>
>>Stuart
>>
>>
>>
>>>I need to specify a 8layer board. Fastest edges on the board are on the
>>>600Mbit LVDS channels : about 500ps. I have two stackups in mind :
>>>
>>> stackup 1 stackup 2
>>>---------------------------------------------------------
>>>L1 routing routing
>>>Substrate
>>>L2 power plane GND
>>>Substrate
>>>L3 power plane routing
>>>Substrate
>>>L4 GND power plane
>>>Substrate
>>>L5 routing power plane
>>>Substrate
>>>L6 routing routing
>>>Substrate
>>>L7 GND GND
>>>Substrate
>>>L8 routing routing
>>>
>>>
>
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