[SI-LIST] Re: PCB Gnd discontinuity on simulation software
- From: Brian Rautio <brian@xxxxxxxxxxxxxxxxxx>
- To: "<Ettore.Ruscino@xxxxxxxxxx>" <Ettore.Ruscino@xxxxxxxxxx>
- Date: Thu, 8 Mar 2012 16:26:38 +0000
All,
Firstly, I'm glad Wolfgang brought up Sonnet lite. I think this is a good
solution for your problem but I was hesitant to bring it up since I am
affiliated with Sonnet, from whom I receive research funding. Sonnet Lite is
very powerful, and "off the record," I'm surprised that they are willing to
give it away for free.
As far as the metal boundary conditions are concerned, I just wanted to add
that this is easy to work around. Firstly, the top cover of the box can be
replaced with an "open" boundary condition in the box setup options. Secondly,
the side walls of the box can be "pushed" away from the metallization in your
circuit by making the box larger. We do recommend using box wall ports for
accuracy, so you can run lines from box wall ports to your circuit and then use
"de-embedding" to remove their effects. A bonus of this entire configuration is
that it will effectively model radiation as well, which, in something like a
fast microstrip backplane is likely non-trivial.
Thanks,
Brian
On Mar 8, 2012, at 6:19 AM, ruscino wrote:
> Hi Wolfgang et all, first of all many tanks for your help to my problem.
>
> My circuit is flexible and has this stack-up:
> 1) kapton
> 2) top layer (routing layer)
> 3) kapton
> 4) copper (gnd layer)
> 5) kapton.
>
> So the circuit is composed of two parts:
> -) a bus, where lvds nets are routed on gnd plane
> (embedded microstrip topology);
> -) the wings where the lvds nets go to the connectors.
> Unfortunately the wings must be of only one routing layer (top) so
> the lvds net topology is no more microstrip. I try to visualize this
> with the draw:
> Wing1 Wing2 Wing3 ...
> || || ||
> || || ||
> || || ||
> ======= || ||
> =============== ||
> ====================== LVDS bus
>
> Sorry if it is unclear.....
> The lvds bus is 40 cm length, the wings are 3 cm each.
> The lvds signal frequency can vary from 40 Mhz to 160 Mhz
> with rise/fall time of about 1-2ns (for the 160Mhz signals).
> I certainly will try to simulate this topology with Sonnet Lite but
> I ask you if it is possible to simulate it with linesim hyperlynx to
> estimate reflection. To know the impedance I built
> two stack-up on two files, one is with ground plane (lvds bus)
> and one is without ground plane (kapton - top layer- kapton).
> These information could be pass to LineSim where I have:
> LVDS driver -> embedded microstrip -> Simple Transmission line-> receiver.
> Is it correct?
>
> Thanks
> Ettore.
>
>
> Il 08/03/2012 08:35, Wolfgang.Maichen@xxxxxxxxxxxx ha scritto:
>> Ettore,
>>
>> actually a full 3D field solver may be a bit overkill; any decent 2.5D
>> (planar) field solver can give pretty accurate answers for split ground
>> planes, and makes model creation easier for an occasional user. As a rule of
>> thumb, routing single ended lines over a split in the reference plane sets
>> you up for a lot of trouble unless both the frequencies involved are very
>> low and the signal rise times are very long. Things are much better for diff
>> pairs which can tolerate breaks much better as long as the two lines of the
>> pair are not spaced too far from each other (1-3 line widths is usually fine
>> with typical PCB dimensions). But only a field solver can give a good answer
>> for a specific case. One place to start could be the free version of Sonnet,
>> called Sonnet Lite - can actually handle such situations and I've used it
>> successfully myself to simulate split grounds. (I'm not affiliated with
>> Sonnet in any way, I'm just a user of Sonnet Lite). One thing to watch out
>> when simulatin
>
> g
>> _single ended_ lines with such a solver are boundary conditions - e.g.
>> Sonnet encloses the model in a virtual metal box, so if you are not careful
>> this box can short your ref planes together, resulting in unrealistically
>> good performance of such a split.
>>
>> Wolfgang
>>
>>
>
>
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