[SI-LIST] Re: Opinions wanted on Signal Integrity analysis tools

Perhaps your best bet is to give a typical problem to each company
and review the answers they provide.

Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Ing. Giancarlo Guida
Sent: Tuesday, January 31, 2006 3:32 AM
To: tom_cip_11551@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Opinions wanted on Signal Integrity analysis
tools

Hi Tom, in my opinion
the portfolio of an SI engineer working at gigabit application
should contain 2 kind of tools.

First a 3d full wave EM solver should be used, in pre-layout analysis,
to fix necessary layout constraint to be used to obtain a clean design.
It should be clear that decision about via, differential via , cut in=20
gnd planes
should not be taken be without the help of a tool .
A 3D solver will help you, in an easy way, to find the best comprise
about strategic problem.
Last but not least a 3D solver can be efficient to analyse power=20
Delivering System,decide where to place
decap capacitor and theyr values...
At the moment I am using CST Microwave Studio, being a time domain=20
solver, it could be very useful for signal integrity problem
A 2D EM solver could also be used to optimize layer stack-up,
spacing and width of traces, material...and so on ( you could find some=20
tools very useful on the web)

Second, a post-layout tool would be necessary when the layout  will be=20
complete
to correct problem introduced during the routing especially if one uses=20
automatic routing.
A typical post-layout tool like the one offered by company such as Zuken

could be a valid help
to find potential SI problem in a complex board and will allow you to=20
perform efficient
time-domain analyisis

A last consideration should be done: these tools need to be introduced=20
in your design flow
and they will have an impact on it.
In my opinion  both pre-layout and post-layout analysis could=20
dramatically improve the "quality" of design flow
and produce a drastic reduction of  the time you, actually, spend=20
debugging your board
but you would need to be careful in tuning the exchange of information=20
among your design flow

Hope this could help

Giancarlo




tom_cip_11551 ha scritto:
> Hi,
>
> At present, I work for a small company that does gigabit design,=20
> pretty much by experiment. If we do not make our return loss=20
> specification, we take some copper away from the ground layer, or do=20
> something else, until we do make it. We may turn the board a few=20
> times but that is the way it goes.
>
> I have done a number evauations of programs that do EM analysis,=20
> such as AWR Microwave Office, CST Microwave Studio and Sonnet EM=20
> Suite.=20
>
> I would like to know if there is an opinion in the group concerning=20
> any other programs that are generally used. For example, I have read=20
> some data about Cadence Specctraquest. Specctraquest, however,=20
> appears to be more model based (pspice) than EM based.
>
> Before I make a proposal to management for capital equipment, I=20
> would like to get more opinions for the SI group.
>
> The main challenge that we have, is the mating of high speed=20
> connectors to the PCB. Sometimes we can get spice models of the=20
> connector, by itself, but that does not do us much good concerning=20
> the mating interface of the PCB pad to the connector pin.=20
>
> Thank You
> Tom
>
>
>
>
>
>
>
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