[SI-LIST] Re: One last question for Chris & Larry re: Power/Decoupling
- From: Larry Smith <Larry.Smith@xxxxxxx>
- To: ctwardy@xxxxxxxxxxxxxxxxxx
- Date: Thu, 22 Jan 2004 10:52:13 -0800
Craig - It is difficult to know the power supply voltage at the
silicon with accuracy at clock frequencies. Sense probes can be wired
into the chip but there are always questions about where on the chip
to place them, how to route them out and how to measure them when you
get out of the package.
We have had real good results at the PCB level and at the top of the
package by using a 50 Ohm coax probe soldered directly to power and
ground. Measurements from an active probe are usually a little
different. The coax probe has very high bandwidth and the
'unprotected' loop where it is attached is very small. You can
certainly measure something on wires that probe into the silicon but I
am not sure that you can believe the results.
There is usually a relationship between the DC voltage and the maximum
frequency that a processor will run. Alex Waizman from Intel has done
some good work in this area. Most of us believe that noise on top of
the DC voltage will decrease Fmax, but this relationship is probably
frequency dependent and difficult to quantify.
It may be possible to inject noise on low power systems, but for 100W
processors, noise injection is difficult at best.
This is a difficult area which is ripe for technical development. I'd
be interested in comments from others on the list for this topic.
regards,
Larry Smith
Sun Microsystems
Craig Twardy wrote:
>
> Hi Larry;
> The thread has talked about the importance of the power supply at the
> Silicon.
> How should the power supply margin be verified at the silicon?
> Can the DC voltage be reduced until the device stops functioning?
> Can noise be injected?
> Can the noise at the silicon be measured?
> Other options?
>
> Craig
>
> -----Original Message-----
> From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
> Sent: January 20, 2004 1:14 PM
> To: Grasso, Charles
> Cc: 'Chris.Cheng@xxxxxxxxxxxx'; 'Charles Grasso'; 'scott@xxxxxxxxxxxxx';
> 'silist'
> Subject: [SI-LIST] Re: One last question for Chris & Larry re:
> Power/Decoupling
>
> Charles - Voltage, frequency and temperature are still major parameters for
> system verification and test of our designs. In addition to that, we
> measure the impedance vs frequency of our PDS from every angle that we can
> including the broad PCB, inside the perforated BGA pattern and from the top
> of the package near the chip if possible. We also measure time domain and
> frequency domain noise (O'scope and spectrum analyzer) from all available
> access points on functioning hardware.
>
> Probably the most important thing we do is compare our hardware measured
> results with our model predictions and tune up the models where necessary.
> This is very much an iterative approach where the best models from our last
> generation are used to predict our next generation. I usually learn
> something new on every new project...
>
> Electromagnetic field solvers and extraction are great but I usually find
> that you have to know the answer before you know how to set up the problem
> to get the answer. :) The hardware keeps you honest and by going back and
> forth between lab and simulation we get a pretty good idea of what is really
> going on.
>
> Let me also comment that the "one size fits all" approach is not likely to
> work in our industry. Different products have current demands and noise
> tolerance. For a class of products, it is probably possible and desirable
> to figure out the best way handling the PDS.
> But even in one product, I see significant differences in the best way to
> handle core and I/O power. There is no substitute for understanding the PDS
> needs for each kind of product (differential, single ended, core, mixed
> analog/logic, etc.), and designing a PDS to meet those needs.
>
> regards,
> Larry Smith
> Sun Microsystems
>
> "Grasso, Charles" wrote:
> >
> > Gentlemen,
> >
> > Irrespective of the Power Distribution approach, the key is system
> > operation. Here's the question. How do go about proving the robustness
> > of your designs? In the old days we used variations of
> > frequency/voltage and temperature. Is that still the case?
> >
> > Best Regards
> > Charles Grasso
> > Senior Compliance Engineer
> > Echostar Communications Corp.
> > Tel: 303-706-5467
> > Fax: 303-799-6222
> > Cell: 303-204-2974
> > Email: charles.grasso@xxxxxxxxxxxx;
> > Email Alternate: chasgrasso@xxxxxxxx
> >
> >
> > -----Original Message-----
> > From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]
> > Sent: Thursday, January 15, 2004 7:57 PM
> > To: 'Charles Grasso'; Chris Cheng; 'Larry Smith'
> > Cc: scott@xxxxxxxxxxxxx; silist
> > Subject: [SI-LIST] Re: Distribution/Filtering/Decoupling Guide The
> > 100Mhz clean cutt off.
> >
> > Well, I will give it a try based on what I now see as a complete
> > picture of what's going on with Larry's example.
> >
> > Disclaimer first
> > Since I was responsible for a lot of packaging and module designs in
> > Larry's company before I departed many years ago, I have to say I have
> > never seen or reviewed or involved in any of the current or whatever
> > future generation package or module he is referring to. Everything I
> > am saying is simply based on what Larry has disclosed in this public
> > forum. If my guess is wrong, please accept my apology.
> >
> > To begin the discussion, I have to requote Zhiping's question below on
> > how to "shift the power integrity problem to the PCB level". I claim
> > there is a hard limit of 100MHz on the package power distribution, by
> > that I mean with the existing number of pins/sockets and package caps
> > and on die decoupling, all the available decoupling charge on the
> > package and die will be consumed and core voltage will start to drop
> > after 10ns of continues current drain on die. Something on the PCB and
> > external DC/DC regulator has to start providing the charge to maintain
> > the voltage level on die. By the same token, due to the exiting
> > impedance at the pins/socket and package, the system (PCB or
> > regulator) cannot reach the Si core power faster than 100MHz. This is
> > based on an optimized pin analysis where I want to provide the least
> > amount of power and ground pins (if you ship a huge volume, like a
> > 100M of them, @ a few cents per pin, you save a LOT of money) that can
> > maintain the minimum core noise level on die. The added benefit of it
> > is you don't need to demand exotic >100MHz decoupling outside the package
> (since it won't help
> > anyways) and you also don't need to over kill your decoupling on package
> by
> > providing <100MHz decoupling bulk caps, just pass that responsibility to
> the
> > system folks.
> >
> > Now let's say you throw in too many power and ground pins on your
> > package. Not only does it cost you money (@ a few cents per pin), it
> > now also starts to perforated your PCB power and gnd planes to the
> > extend that the PCB to package impedance starts to pick up (shifting
> > below 100MHz). Now you really need to have a thin core PCB to lower
> > the impedance back to equal the case when you have less power/ground
> > pins with a smaller package. But in a sense, this is exactly what
> > Zhiping was asking for, shifting some of the integrity problem to the
> > PCB level. You can over design to an extend that what happen in the
> > PCB really start to impact the package performance.
> >
> > It's your choice, too many pins and you will need BC and cost you
> > $$$$$$, just enough pins and you don't need BC and save you some $
> > also. But if you don't have enough pins, you are dead and no system or
> > PCB design can save you.
> >
> > As a side note for those who want to built benchmark system design to
> > evaluate system to package distribution, good luck ! If you think you
> > can pick up something as subtle as the above, my hats off to you. I
> > have enough trouble doing a unique case where I know everything ahead
> > of time.
> >
> > Same old song here, there is no need for BC. Hey, that may be in my
> > second broken record.
> >
> > -----Original Message-----
> > From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]
> > Sent: Thursday, January 15, 2004 5:34 PM
> > To: Chris.Cheng@xxxxxxxxxxxx; 'Larry Smith'
> > Cc: scott@xxxxxxxxxxxxx; silist
> > Subject: Distribution/Filtering/Decoupling Guide The 100Mhz clean cutt
> > off.
> >
> > Chris, Larry et al...
> >
> > Can you please explain the 100MHz clean cut so often mentioned in ths
> > thread? Is it bandwidth (i.e related to rise time?) is it the crystal
> > or...
> >
> > Puzzled.
> > Chas in Colorado..
> >
> > -----Original Message-----
> > From: zhiping yang [mailto:zhiping@xxxxxxxxx]
> > Sent: Tuesday, January 13, 2004 5:55 PM
> > To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > Subject: Re: [SI-LIST] Re: Power Supply
> > Distribution/Filtering/Decoupling Guide]
> >
> > Hi Chris,
> >
> > Thank you for sharing your thoughts and Very good points about the
> > power integrity.
> >
> > One comment about your "total system approach". Technically speaking,
> > it is best to put the equal amount of efforts on the die, package and
> > PCB power distribution since they are equally important in the
> > complete power delivery system. More important, the PCB COULD NOT fix
> > the problems with the die and package power delivery systems in some
> > cases.
> >
> > In the real word, when cost and $$ is involved, the trade-offes must
> > be made, so the design may not be optimized in technical side. For
> > example, due to the high cost of die size increase and package
> > limitations, it may be more cost effective by shifting the power
> > integrity problem to the PCB level at a certain degree. This may
> > require using BC or more decoupling caps on the board, but it could
> > still be cost effective from the "total system" point view.
> >
> > This is my $0.02 input. Thanks.
> >
> > Zhiping
> > ------------------------------------------------------------------
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