[SI-LIST] Re: One last question for Chris & Larry re: Power/D ecoupling

Hi Tom, Craig,
Tom using a static I/O cell is a neat way to look at the power supplies for 
that portion
of the I/O array but my experience has been that the I/O cells are either not
connected to the same power supply as the core or that they have separate 
routing.
Though I have not built any silicon for a few years so maybe things have 
changed.

Having said that; this trick is still a nice way to probe for SOS problems 
in the
ground and power of the I/O cells.   I used this trick (treating a couple 
static I/O
cells as signal multiplexors) once on a Xilinx design and once about the 
turn of the
century on a 68000 CPU in a DIP 64 package.
The trick worked very well to catch the I/O power bus bounce inside the package
during an 0xFFFFFF to 000000 address bus transition.

Please excuse the nostalgia.... nice to pass around the silicon war stories 
occasionally.

best regards,
Kellee


At 05:20 PM 1/26/2004, Tom Biggs wrote:
>I've heard this trick:
>If you are lucky (or can configure it) so there are two output pins on
>the IC where one is driven high, and the other driven low, then you can
>use these pins as probes into the internal power/ground planes. The
>probes will be through turned-on FETs, so I'm not sure what affect this
>has on the accuracy for your needs.
>
>     -tom
>
>-----Original Message-----
>From: Craig Twardy [mailto:ctwardy@xxxxxxxxxxxxxxxxxx]=20
>Sent: Monday, January 26, 2004 4:40 PM
>To: Chris Cheng; 'Larry.Smith@xxxxxxx'
>Cc: 'silist'
>Subject: [SI-LIST] Re: One last question for Chris & Larry re: Power/D
>ecoupling
>
>
>Hi Chris;
>Is there a trick to getting the pins that tap core power and gnd? I have
>asked for this before and was given all sorts of reasons Why it cannot,
>could not and will not be done.
>
>Craig


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