[SI-LIST] Re: On-die caps for IO supply

The last std cell design I worked on was 90nm and had a DDR2-533. The 
vendor provided a scalable model for the on-die transient and IR voltage 
drop. As I recall it included die and package parasitics. We added on-die 
I/O capacitance until we meet the vendor's release requirements 
(reasonable IMO) for on-die droop/noise. Don't remember what the 
capacitance was that we ended up with per driver, but by using a special 
on-die cap, we managed to get a lot more than I thought could be possible. 
The results looked good in the lab post-fab.  In any event, I don't see 
how you can proceed without detailed simulations by you or your 
semi-vendor?
best regards and good luck


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