[SI-LIST] Re: [OFF TOPIC] SMD Land patterns
- From: cadpro2k@xxxxxxxxxx
- To: <si-list@xxxxxxxxxxxxx>
- Date: Tue, 28 Jan 2003 11:12:44 -0800
Hi,
Very good write-up Jeff. Ditto to all you say.
One follow on, the IPC-SM-782 revised version is being developed on
http://www.pcbstandards.com with the excellent cooperation of Tom
Hausherr (Windriver Systems, San Diego). What Tom has done is worked
with IPC to develop a "more current" land pattern design guide. Tom has
worked up a land pattern calculator that follows almost exactly what IPC
desires, other than he's taken it the next step and created three
categories of patterns, LEAST, NOMINAL and MAXIMUM criteria. These would
cover what you term as GENERIC, BROAD and NARROW. Tom has a preliminary
calc on the site you can download and view. He's worked very hard with
Dieter Bergman and IPC to meet their "desires". Have a look.
What Tom has available is a PADS library (Metric is free, INCH will cost
you) based on pcbstandards.com standards (all three categories). An
allegro based library is in development, and I believe there is another
cad tool library also (Zuken maybe?). Have a look if you're interested.
As for a "factory specific" library, that is much more involved. You
need a very competant manufacturing engineer that can help determine
land pattern design. IT can be done, ask Qualcomm, Nokia, Motorola (get
my drift... $$$$$$$$$)
Good day.
Mitch
---------Included Message----------
> Date: Tue, 28 Jan 2003 12:55:22 -0500
> From: "Jeff Seeger" <jseeger@xxxxxxxxxxxxxx>
> Reply-To: <jseeger@xxxxxxxxxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: [OFF TOPIC] SMD Land patterns
>
>
> Martin Euredjian wrote:
> >
> > Going beyond raw specifications I'm trying to understand some
of the choices
> > made when designing land patterns for various types of SMT
devices.
> >
> > snip <
> >
> > So, rather than actual footprints I am looking for any kind of
study/paper
> > that looks into the consequences of varying the geometry of the
patterns.
> > In other words: How does pattern geometry affect such areas as
soldering,
> > rework, reliability, testing, manufacturing, etc.?
>
> Martin,
>
> The problem with footprints is the answer is in shades of
> grey rather than black-or-white. The change from one var-
> iation to another does not necessarily result in problems,
> but does move the yield in terms of DPMO.
>
> Having worked with IPC-SM-782 from inception as well as a
> number of CEM and OEM specific guidelines we've come to
> think of footprints in levels of qualification:
>
> generic (the part will attach, data sheet)
> broad concencus (IPC, "reasonable yield" nearly anywhere)
> narrow concencus (OEM negotiated with multiple CEMs)
> factory specific (CEM authored)
>
> As you move down this list you can expect higher yield if
> you are in the matched manufacturing environment. Aspects
> such as rework and inspection access are more an issue in
> determining whether your product is disposable post-test,
> while area reserved for testability prevents fixture or
> component damage.
>
> We try to start with JEDEC package types and confirm them
> to IPC (or other required) specification. The destination
> is really IPC-610 and/or J-STD-001. Close the loop (very
> important) with manufacturing dialogue and inspection.
>
> Hope this perspective is useful,
> --
>
> Jeff Seeger Applied CAD Knowledge
Inc
> Chief Technical Officer Tyngsboro, MA
01879
> jseeger "at" appliedcad "dot" com 978 649
9800
> Printed Board Implementation Services since 1983
>
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