[SI-LIST] Re: Non-monotonic
- From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 31 Jan 2002 09:14:05 -0500
If a signal is driven from IC#1 to IC#2 and IC#3,
and if IC#1 and co-located series resistor are intended to match the
characteristic impedance of the transmission line,
and IC#3 is on the far end with IC#2 somewhere in the middle,
then the waveform at IC#2 is expected to be non-monotonic, or have a
plateau or degraded edge rates.
You might be able to fix it by removing the series resistor and making
IC#1 strong enough to cause "incident wave" switching (Zout << Zo of the
transmission line), but then you might need a termination at IC#3, or
else you could get severe overshoot and ringing.
Alternatively, you might fix it by moving IC#2 next to IC#3, so that
both are at (or very close to) the end of the trace. Or if monotonic
edges aren't needed at IC#3, route from IC#1 to IC#3 and then to IC#2.
For most devices, clocks and non-clocked control signals are the ones
needing clean edges; other signals could be sloppy just as long as they
stabilize in time to meet whatever Setup and Hold time requirements
there are. Sometimes it is good to worry about all signals on memory
devices, because some memory devices are not exactly "ideal" with
respect to ignoring their input signals outside the Setup/Hold time
window where signals are sampled. Also, any signal that is not at a
valid logic level for a long time, risks causing metastability,
self-oscillations, or over-heating, depending on the device.
Andy
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