[SI-LIST] Newbie board question

(As this is a newbie question; apologies to those not
interested.)

Hi All,

I have a nearly complete beta design of a high
speed board. I've tried to follow principles
gleaned from this list and other sources,
but since my background is in CS (no grumbling=20
please :) ), I thought it would be prudent to=20
run my design past any altruistic readers here=20
just to see if there are any obvious high level=20
issues that I should be concerned with.

Goal

FPGA (Virtex-II) based signal processing board=20
w/ core clock running @ 200 MHz. Basic signal=20
is 12 bits @ 200 Msps. This is for academic=20
research, so I'm more worried about correctness=20
and low number of spins than I am about optimizing=20
component cost etc.

I/O

Input1:  12 bits LVDS @ 200 MHz
Output1: 2x12 bits CMOS @ 100 MHz (interleaving gives=20
         basic signal)
(these I/Os will eventually be an intra-board signal,=20
inter-board in prototype)
        =20
Input2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
Output2: 6 bits LVDS @ 400 MHz (DDR of basic signal)
(these I/Os are running inter-board over LVDS/SCSI cable
w/ VHDCI connectors)

Stackup

Layer   Type   Separation (mils)
1       LVDS
               8
2       GND
               8
3       VCC 1.5 (powers FPGA core)
               4.5
4       VCC 2.5 (powers LVDS)
               8
5       CMOS (flooded w/ GND where possible)
               4.5
6       VCC 3.3 (powers CMOS)
               8
7       GND
               8
8       LVDS

outer copper 1 ounce, inner 0.5 ounce

Decoupling Caps
I have over 1 cap/power pin since I'm
trying to err on the side of caution.

(Not showing caps near/required by voltage=20
regulators)
VCC
1.5  2.5  3.3   Capacitor (uf)
------------------------------
 4*  10*   4*    0.0022=09
 4*   6    6     0.022
 2    6    2     0.1
 2    2    2     1
 1    1    1     4.7
 1    1    1    47
* =3D located under FPGA in middle of ball grid

I'm using blind vias on the FPGA's center ground pins
to create room underneath. This requires blind
vias in two directions though (top for FPGA GND,=20
bottom caps fanout). Naturally if I could get by=20
with no-blind vias and only a couple caps directly=20
under, that would be great. Since I really don't
know if that's OK or not, I'm erring on the side of=20
caution; I'd rather have a more expensive initial=20
spin than a respin/power plane debug.

Traces

Used National's app notes for LVDS to determine differential
pair spacing etc. LVDS trace sep is 5 mils. I'm using guard
traces for all high speed signals (not sure if necessary...).

Banking

I've split the interleaved 12-bit 100 MHz CMOS signals
across two IO banks each so that each bank always has
6 (potential) changing IOs. I'm hoping to reduce
simultaneous switching IOs and ground bounce issues here.

Design Success Criteria

core clock speed
200 MHz =3D ideal
150 MHz =3D near ideal
100 MHz =3D fair
50 MHz =3D semi-functional
< =3D expensive toy

Again, I'm looking for high-level comments (even
"you'll never succeed" would be OK :) ) and not
expecting a detailed critique.

Thanks in advance!

Glenn


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