[SI-LIST] Re: Need advice on basic 6-layer stackup
- From: steve weir <weirsi@xxxxxxxxxx>
- To: GrahamDavies@xxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Sat, 30 Apr 2005 16:13:54 -0700
Graham, I suggest that it is probably a good time for you to search through
the wealth of information on the WWW, as well as purchase at least one or
two books on signal integrity. There are many good titles out there. As
to your specific concerns on series terminations and busses, your concern
is valid for timing strobes like clocks. For bussed data, series
termination works very well over a broad range of applications. If you are
the PCB designer, I suggest pushing back on the design engineers to do
their signal integrity homework. If no one in your shop has the
experience, find a colleague, or hire a consultant. If the design is
simple and low-tech, it won't cost a lot to have a competent consultant put
you on track.
Since you are running slow busses, you should have a lot of leeway with
timing. Consider that PCI has been fantastically successful with much less
than pretty signaling. A timing budget that includes the effects of cross
talk needs to be built. You may find that you have gross margins that let
you get away with murder. But you will not KNOW until someone DOES THE
HOMEWORK.
For your example of a 10 inch trace if the rise time is 10ns or less, ( and
it is a very safe bet that it is ), you have a transmission line, and
failing to model that trace as a transmission line will give you the wrong
answer.
I strongly disagree with SPS SGS as a signaling improvement. It does
address warpage. Can you make it work? DO THE HOMEWORK. But consider it
against what is really SGS SGS, where L3 S is gridded power. This uniform
stack up doesn't warp either. The bottom three layers of both stack ups
are identical.
So what are the differences:
1) Less Cu for power, resulting in higher DC loss as gridded on L3 in SGS
SGS, than the solid plane in SPS SGS.
2) Much lower inductance for power in SGS SGS. Assume 50% fill density,
this is equivalent to solid planes separated by 7 mils, whereas SPS SGS
would be separated by about 52 mils a > 7:1 difference. You would have to
drop to a ridiculous 4 mil lines on a 50 mil grid to end up with as high a
power spreading inductance in SGS SGS as SPS SGS.
3) Trivial return path management in SGS SGS that allows very simple
autorouter rules. SPS SGS requires more care
I would ask the person promoting SPS SGS to explain to you what they
believe it buys you.
Steve
At 08:22 PM 4/29/2005 +0000, Graham Davies wrote:
>--- In si-list@xxxxxxxxxxxxxxx, steve weir <weirsi@xxxx> wrote:
>
> > Graham, you are welcome.
>
>If I wear out my welcome, just let me know! From other posts, I seem
>to be on-topic and not at too elementary a level.
>
> > Source series terminated signals
> > tend to be very easy to drive
> > with modern logic.
>
>My understanding of source termination is that it's just about
>perfect under two conditions. First, the transmission line impedance
>of the traces is close to the source impedance of the driver. If it
>is higher, you end up sprinkling resistors all over like ground
>pepper on a Ceasar salad. Second, your signals have to be point-to-
>point. On busses, intermediate connections see the signal rise half-
>way on the outgoing wave and then the rest of the way when the
>reflected wave comes back. So, there you are sitting right at the
>logic threshold for a while just waiting for a little crosstalk to
>mess you up.
>
>This design of mine has a lot more bussed signals that point-to-
>point, so I'm cautious about thinking of series termination as a
>silver bullet.
>
> > EMC generally improves with
> > thinner dielectric.
>
>Understood.
>
> > Fifty ohms is a very common
> > transmission line impedance.
> > So, I don't see a downside
> > to a 50 ohm system. This is
> > the norm today.
>
>OK, fair enough. I'm personally more fond of advice that reads "Do
>this because [explanation]" than "Do this because it's what everyone
>else does" but knowing what everyone else does is, for me, a step in
>the right direction, so thanks!
>
> > Cross talk is a function of the
> > ratio of the trace horizontal
> > separation to the height.
>
>Understood again. It's only this impedance business that's giving me
>pause. In all other respects, closer seems to be better.
>
> > If you want to reduce cross talk,
> > you can space the traces out,
> > possibly creating routing problems,
> > or go with thinner dielectric. So,
> > once again, I don't see any good
> > motivation to increase the
> > dielectric thickness.
>
>It's only the difficulty of driving the low impedance of the traces
>with the 1999-vintage chips on the board. I can't space out the
>traces and expect to route on two-and-a-half layers. I am prepared
>to squeeze in grounded guard traces on either side of critical traces
>like clocks where they run parallel to other traces.
>
> > ... copper plane ... not matched ...
>
>Other messages in this thread have me sorted out about possible
>warping and what to do about it. Your layer swap seems good too.
>
> > ... I suggest AWR's TxLine ...
> > It shows much closer to 50
> > ohms than the calculator you
> > are using.
>
>It sure does. So, do I trust TxLine or the University of Missouri-
>Rolla? I need a third opinion. I will report back if I find one.
>
> > Here are some clues as to whether
> > controlled impedance is a good idea:
>
>Like Ross Perot, I'm all ears.
>
> > Do you have rise or fall times
> > that are substantially shorter
> > than 6X ( ie 1ns / inch ) the
> > length of the traces they drive?
> > If so, you will start to see
> > substantial wave effects, the
> > lower that ratio goes.
>
>OK, I'm not sure I understand this. I have a trace that is 10 inches
>that is giving me trouble. So, should I compare the rise time to 10
>ns or six times that or one sixth of that? I think 10 ns. This is
>about what it is and the signal is horrible. Additional series
>resistance helps a bit, but this is a multi-point net so I'm not
>kidding myself I have series termination here. All I think I'm doing
>is slowing down the edge.
>
>Basically, this is where I came in the first place. This board needs
>to be redesigned. I'm looking for advice on the stackup. What I've
>got is this:
>* it's not a bad stackup (the second one, not the first)
>* it would be better with the power and internal routing layers
>swapped
>* I should fill on the internal routing layer and grid the power
>layer to balance copper and avoid warpage
>* 50 ohms trace impedance is a common choice
>* nobody agrees with me that I should go higher to make the traces
>easier for the chips to drive
>* two impedance calculators give significantly different results
>
>Off-list, someone has suggested that I'm being led to over-engineer
>this board because of assumptions I've failed to clarify. So, here
>is some additional data:
>
>1) The board should be 0.062 in thick. I'm not really sure how it
>would help me to change this, though.
>
>2) I don't have any fast-switching (sub 1.5 ns) signals, so my
>assumption that I need the power to ground plane capacitance to help
>with decoupling may be false. I've already agreed to grid the power
>plane. Off-list it is suggested that I change the stackup to S-P-S-S-
>G-S and forget about having power and ground planes close together.
>
>3) There is also the assumption that I need to use ground for signal
>returns. I understand that power can be used as a return if there is
>sufficient decoupling. My issue with this is that when a signal moves
>from a layer referenced to ground to a layer referenced to power you
>now need not just a via but a decoupling capacitor close by so that
>the return path can go between plane layers. With components only on
>the top (for cost reasons) I'm wondering if I have room for this.
>
>Graham.
>
>
>
>
>
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