[SI-LIST] Re: Need advice on basic 6-layer stackup

• From: "Graham Davies" <GrahamDavies@xxxxxxxx>
• To: si-list@xxxxxxxxxxxxx
• Date: Fri, 29 Apr 2005 20:22:24 -0000

```--- In si-list@xxxxxxxxxxxxxxx, steve weir <weirsi@xxxx> wrote:

> Graham, you are welcome.

If I wear out my welcome, just let me know! From other posts, I seem
to be on-topic and not at too elementary a level.

> Source series terminated signals
> tend to be very easy to drive
> with modern logic.

My understanding of source termination is that it's just about
perfect under two conditions. First, the transmission line impedance
of the traces is close to the source impedance of the driver. If it
is higher, you end up sprinkling resistors all over like ground
pepper on a Ceasar salad. Second, your signals have to be point-to-
point. On busses, intermediate connections see the signal rise half-
way on the outgoing wave and then the rest of the way when the
reflected wave comes back. So, there you are sitting right at the
logic threshold for a while just waiting for a little crosstalk to
mess you up.

This design of mine has a lot more bussed signals that point-to-
point, so I'm cautious about thinking of series termination as a
silver bullet.

> EMC generally improves with
> thinner dielectric.

Understood.

> Fifty ohms is a very common
> transmission line impedance.
> So, I don't see a downside
> to a 50 ohm system.  This is
> the norm today.

OK, fair enough. I'm personally more fond of advice that reads "Do
this because [explanation]" than "Do this because it's what everyone
else does" but knowing what everyone else does is, for me, a step in
the right direction, so thanks!

> Cross talk is a function of the
> ratio of the trace horizontal
> separation to the height.

Understood again. It's only this impedance business that's giving me
pause. In all other respects, closer seems to be better.

> If you want to reduce cross talk,
> you can space the traces out,
> possibly creating routing problems,
> or go with thinner dielectric.  So,
> once again, I don't see any good
> motivation to increase the
> dielectric thickness.

It's only the difficulty of driving the low impedance of the traces
with the 1999-vintage chips on the board. I can't space out the
traces and expect to route on two-and-a-half layers.  I am prepared
to squeeze in grounded guard traces on either side of critical traces
like clocks where they run parallel to other traces.

> ... copper plane ... not matched ...

warping and what to do about it. Your layer swap seems good too.

> ... I suggest AWR's TxLine ...
> It shows much closer to 50
> ohms than the calculator you
> are using.

It sure does. So, do I trust TxLine or the University of Missouri-
Rolla? I need a third opinion. I will report back if I find one.

> Here are some clues as to whether
> controlled impedance is a good idea:

Like Ross Perot, I'm all ears.

> Do you have rise or fall times
> that are substantially shorter
> than 6X ( ie 1ns / inch ) the
> length of the traces they drive?
> If so, you will start to see
> substantial wave effects, the
> lower that ratio goes.

OK, I'm not sure I understand this. I have a trace that is 10 inches
that is giving me trouble. So, should I compare the rise time to 10
ns or six times that or one sixth of that? I think 10 ns. This is
resistance helps a bit, but this is a multi-point net so I'm not
kidding myself I have series termination here. All I think I'm doing
is slowing down the edge.

Basically, this is where I came in the first place. This board needs
to be redesigned. I'm looking for advice on the stackup. What I've
got is this:
* it's not a bad stackup (the second one, not the first)
* it would be better with the power and internal routing layers
swapped
* I should fill on the internal routing layer and grid the power
layer to balance copper and avoid warpage
* 50 ohms trace impedance is a common choice
* nobody agrees with me that I should go higher to make the traces
easier for the chips to drive
* two impedance calculators give significantly different results

Off-list, someone has suggested that I'm being led to over-engineer
this board because of assumptions I've failed to clarify.  So, here

1) The board should be 0.062 in thick. I'm not really sure how it
would help me to change this, though.

2) I don't have any fast-switching (sub 1.5 ns) signals, so my
assumption that I need the power to ground plane capacitance to help
with decoupling may be false. I've already agreed to grid the power
plane. Off-list it is suggested that I change the stackup to S-P-S-S-
G-S and forget about having power and ground planes close together.

3) There is also the assumption that I need to use ground for signal
returns. I understand that power can be used as a return if there is
sufficient decoupling. My issue with this is that when a signal moves
from a layer referenced to ground to a layer referenced to power you
now need not just a via but a decoupling capacitor close by so that
the return path can go between plane layers. With components only on
the top (for cost reasons) I'm wondering if I have room for this.

Graham.

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