Hello So far all the modelling I have done has been on PCB's, backplanes and packages. Recently there has been a need to model on chip interconnect structures in the 0.13um and 90nm technologies. I was wondering if there is any major differences in setup for semiconductors (Si not being a pure dielectric, small size of the nets etc.) Are there any differences in boundary conditions to be used in SI2D or HFSS? Any other unusual effects I should watch out for. Any input would be appreciated. Thanks Anil Anil Pannikkat MTS Package Development * : 408-544-7542 Altera Corporation Fax: 408-544-6404 101, Innovation Drive, M/S 4202 *: apannikk@xxxxxxxxxx San Jose, CA 95134 *: http://www.altera.com ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu