[SI-LIST] Middle (Star) Termination

Can anyone please provide a brief explanation regarding the theory of a middle 
termination scheme?
In the book" High Speed Digital Design" by Johnson&Graham the topic seems to be 
glossed over. It essentially says that providing resistors connected in the 
middle of a star network that have impedance of 1/3 Zo work by halving the 
voltage at the node. I've used Hyperlynx to simulate this arrangement and it 
works well. I've searched the web and haven't found a satisfactory explanation.
 
Thanks in advance.
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