[SI-LIST] Memory bus datapattern

Hi everybody,
I have a problem with how to define a reasonable worst case datapattern on a
DDR data bus to calculate crosstalk and SSN on the power supply.

Should I assume that all 32 bits start in a low/high state and change
simultaneously or is there a better choice?
I mean, all bits will not change at the same time, which means that I will
design towards a worst worst case instead of a real worst case.
Have someone made some statistical analysis of how many bits are high/low
and how many will change state every cycle?

Any ideas?

BR
Peter

PS I'm a Homer fan if someone wonders


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