[SI-LIST] Meeting Announcement: IPC-SVC on Nov. 11 in San Jose
- From: Bob McCreight <bobmccr8@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 4 Nov 2003 16:28:54 -0800 (PST)
Meeting Announcement: IPC-SVC on Nov. 11 in San Jose
The IPC Designers Councils' Silicon Valley Chapter
will
be meeting on Tuesday, November 11 at Mentor Graphics
in San Jose (1001 Ridder Park Drive).
Time: 11:30AM - 1:30PM
$1 for members; $5 for non-members
RSVP required > send to SV_IPC@xxxxxxxxx
DOOR PRIZE: $25 IPC Publication Certificate
Topic: Advanced Placement Techniques, a key to success
Speaker: Patrick Jabbaz
Patrick Jabbaz is a Sr. Circuit Board Layout Engineer
with InkraNetworks (California). Patrick Holds a
Degree in Electrical Engineering has been designing
Printed Circuit Boards for the past 12 years. He is a
current board member of the Silicon Valley IPC
Designer's Council and past board member of the
Houston IPC Designer's Council and has received his
IPC Designers Certification.
Objective: To give an insight depth on all aspect of
Component placement
Topics covered
1- Overview of Placement Strategy
Identified the fixed component locations as well as
Mechanical keep-outs
2- The technology involved
Is this RF or Digital, or Both, are thermal issues a
concerned?
3- Types of products
Is it small form factor, a PC-card, or a huge Telco
board?
4- Quick evaluation
Place the key parts, and feel how the rest just falls
into place
5- 3 quick ways to Setup the signal flow
Having a look at the rats-nets, flow of signal routing
channels and the board layer count.
6- Thermal considerations
Create air flow channels, analyze hot spots
7- Ready for routing
Power delivery checked, analyzed routing channels,
Fan-out's, RF sections fixed and approved, timing
rules met.
RSVP REQUIRED!
http://dcchapters.ipc.org/svc/
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