[SI-LIST] Re: Maximum Frequency for S-parameter Extraction of Board Power Plane

hi guys,

Yes, package PDN tends to be inductive and filter higher frequency noise
from a chip that may exist on a board PDN. To characterize on-chip core PDN
switching noise in chip-centric analysis one can often deemphasize frequency
domain behavior of the board above the range Steve mentions. A very good
thing because otherwise each chip would need to have its PDN crafted for
different end system applications.

However, IO PDN noise may be a different story. You are no longer looking at
many hundred or even thousands of VSS/VDD pins but tens or low hundreds of
IO power pins. You don't have full power planes and in some cases there may
not be a huge difference between the routing of IO power nets versus IO
signal nets. Not just on the board, but also in the package, your SI and PI
effects are much more tightly coupled. Take for example SSO. SSO would not
exist if only proximity coupling amongst signals but is dominantly a PDN
issue coupled to the signals. The noise coupled from PDN to signals in the
board has a high bandwidth path along the IO signal nets through even the
most inductive package.

Also, if you are designing the PCB instead of the chip you may well be
concerned with PDN behavior above where the package limits its effect for
on-chip core PDN noise. PDN resonances greatly increase the coupling between
SI and PI in a quite global sense across the board. They also dominate many
digital system EMC issues. Your package might imply little on-chip influence
beyond a few hundred MHz, but you've still got to pass FCC specs well above
this.

As always, be careful what you choose to ignore and for what applications
your assumptions apply.

cheers,
 -Brad

> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> Sent: Wednesday, May 18, 2011 4:24 AM
> To: Rajan Hansa
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Maximum Frequency for S-parameter 
> Extraction of Board Power Plane
> 
> At 3X the package cut-off:
> 1. You are well-past resonance that occurs just below the cut-off.
> 2. The amount of energy transferred is typically down 20dB.  
> The impedance of the PCB above this point will have very 
> little impact on the power delivery in the IC package.  You 
> could simulate to a higher frequency but with little 
> improvement in result accuracy or actionable information.  
> You could also simulate only to a lower frequency, but with 
> rapidly increasing uncertainty near what is usually the 
> highest, or close to the highest impedance seen by the die.
> 
> Steve.
> On 5/18/2011 4:12 AM, Rajan Hansa wrote:
> > Thanks Steve for being always prompt in reply !!
> > Can you please explain how you have got this magical figure, 3 X 
> > highest package cut-off frequency ? Why It's not 2 X or 1 X ??
> > Rajan
> >
> > On Wed, May 18, 2011 at 4:21 PM, steve weir <weirsi@xxxxxxxxxx 
> > <mailto:weirsi@xxxxxxxxxx>> wrote:
> >
> >     If you are concerned only with power delivery then 
> simulate to 3X the
> >     highest package cut-off frequency of any device you are 
> concerned with
> >     that is attached to a given power rail.
> >
> >     Steve.
> >     On 5/18/2011 3:44 AM, Rajan Hansa wrote:
> >     > Hello All,
> >     >
> >     >
> >     > I have got a PCB database of one Ethernet Board and I have to
> >     extract
> >     > s-parameter for all power plane from voltage 
> regulator to  power
> >     pin of
> >     > chip package. The Board database includes all decap.
> >     >
> >     >
> >     >
> >     > As we know extraction time is directly related with maximum
> >     frequency So
> >     > while setting maximum frequency for s-parameter 
> extraction, I am bit
> >     > confused, I would like to know that do I need to set knee
> >     frequency ( Fknee
> >     > = 0.35/Trise) as maximum frequency OR for board level 
> simulation we
> >     > shouldn't care knee frequency.
> >     >
> >     >
> >     >
> >     > As per my understanding, package inductance won't allow very
> >     high frequency
> >     > component (switching current component which depends on Trise
> >     !!) to travel
> >     > to board from chip so voltage regulator in board will 
> never see
> >     those high
> >     > switching current so I shouldn't simulate/extract s-parameter
> >     till knee
> >     > frequency.
> >     >
> >     >
> >     >
> >     > What's expert view on this ?
> >     >
> >     >
> >     >
> >     > Rgds,
> >     >
> >     > Rajan
> >     >
> >     > 
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> Steve Weir
> IPBLOX, LLC
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> Reno, NV  89501
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