[SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth

This is a well thought question I have repeatedly asked in this list and 
getting no where.
I know there are active list member here participating these spec committees, 
lectured and wrote books about it but refused to stand up and defend the spec. 
Not in person, in his lectures nor in si-list.
I think it comes down to your view of the over SerDes architecture. 
Some people believe the source reference clock is the original evil of the real 
PLL jitter between the TX and RX side. If that's what you believe, slowing down 
AND matching the bandwidth between the TX and RX PLL make sense. i.e. you are 
addressing the jitter transfer issue. There are certainly lousy clock source 
out there especially when you are dealing with these high fan out zero delay 
PLL buffers. But at least it is a piece of isolated silicon most probably 
surrounded by a ton of analog power filters.
You will be pulling hair out of you head if you believe power noise on your PLL 
will impact more on your jitter than the incoming clock source. i.e. jitter 
accumulation. And with real life SerDes (not the demo some silicon house try to 
show you in their test chip), you are dealing with a piece of analog circuit 
buried deep inside a noise logic core that generate all kinds of digital noise. 
Personally I will be more worry about that than the jitter transfer problem. 
But that's just me.
Now add to that a third consideration. With the limited implementations of 
multi-giga bit CDR I am aware of, most if not all of them have a dual or 
multi-loop architecture. Most of the standards do not source multi-giga Hz 
reference clock. It usually end up with something like 100 or 150MHz clock 
delivered. The CDR multiply up the reference clock to a higher frequency and 
then generate multi-phase output for the inner phase interpolator (e.g. bang 
bang phase detector) to track the incoming data. What the confusion is whether 
the Fbaud/1667 is refer to the outer slower PLL bandwidth or the inner bang 
bang loop. I believe the low bandwidth is referred to the outer PLL which is 
reference to the 100/150MHz clock. So if you do the number, the PLL bandwidth 
is 30x slower to begin with. Factor in the phase margin requirement, Fbaud/1000 
is not to bad a loop bandwidth to begin with.
That said, I have seen some new slick CDR reference clock design that have 
multi-loops involving DLL that have inherited stable phase margin with much 
higher bandwidth possible. Why limit such circuit potential by imposing such a 
low spec is beyond me.


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Steve Waldstein
Sent: Monday, September 15, 2008 4:08 PM
To: 'steve weir'
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth



Steve,

Thanks for your answer but I'm still a little perplexed. In a PLL the loop
bandwidth typically wants to be about a factor of 10 lower than the
transition density in the reference clock to the PDF. But pushing the
bandwidth lower will allow a noiser (more jitter) reference clock at the
expense of seeing increased VCO jitter. The opposite it true where you use
a
higher loop bandwidth to clean up the VCO but you suffer from clock noise
passing through the loop bandwidth that causes output jitter.

I'm sure there is a similar analogy for the CDR. A lower loop bandwidth
should produce a cleaner recovered clock but makes the loop less agile to
data changes. A higher loop bandwidth makes the loop more agile but
produces
more jitter on the output.

Lets use an example for discussion. XAUI has Fbaud = 3.125 Gb/s and 8b/10b
(or 10Q) encoded. Yet its corner frequency is set at 3.215/1667 = 1.87
MHz.
Is this because XAUI want to recover a clock and recreate it to some kind
of
PPM accuracy similar its input spec of +/- 100 PPM? I know SONET had
repeaters in it where the clock recreation was important but on most
serial
links that's not the case. So since you said Fbaud/30 was typically
sufficient to recover the day why burden the receiver with such a narrow
loop bandwidth?

Is it really related to the fact that at +/- 100 PPM one skip is inserted
every 5000 symbols so the 1667 provides margin to this by a factor of 3?

I've also seen calculation that predict the jitter of a sinusoidal
modulation of the carrier that relate to the equivalent PPM. It the corner
really set to handle this type of issue? And not ability to recover the
data?

I know these are a lot of questions but your answer doesn't help
understand
why these standards have chosen such a low loop bandwitch.

Steve W.


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On
Behalf Of steve weir
Sent: Sunday, September 14, 2008 10:38 PM
To: Steve Waldstein
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Majic Fbaud/1667 for CDR bandwidth

Steve the loop B/W has to do with:

The available repetitive data rate.
Reasonable phase / gain margin for the loop filter.

Each of the various data transmission standards are different in the way
that they can mess up a CDR, with the net result that many standards
need very tall ratios between Fbaud and Fcorner.  Basically, you can
easily achieve very stable operation by setting Fcorner = Frepeat / 5.
With some care you can set it to Frepeat / 3, where Frepeat is the
guaranteed lowest repetitive full 1-0 cycle.  For a pure 8B/10Q coded
link, Fcorner can be as high as Fbaud / 30 and work well.

As Chris Cheng has bemoaned, TIE and jitter in general both get worse
with taller ratios as the VCO drifts ( or is disturbed by things like
PDN noise ) over more bit intervals without the benefit of corrective
feedback.

Steve.

Steve Waldstein wrote:
> I know many serial specifications place the corner frequency of a CDR at
> Fbaud/1667. I also know that the FC-MJSQ discusses how this was shifted
from
> the Fbaud/2500 established for SONET. What I can't find is a good
discussion
> on how to set CDR loop bandwidth for new serial specification. It
appears
> there's some relation the desired frequency accuracy or ppm but haven't
> found a good derivation.  Can anyone provide a good reference relating
to
> choosing loop bandwidth based on desired output jitter or what ever else
> helps set this corner frequency.
>
>
> Thanks.
>
>
>
> Steve
>
> __________________________________
>
> Steve Waldstein
>
> E-mail: swldstn@xxxxxxxxx
>
> Mobile: (207) 749-6260
>
> Home:  (207) 885-0594
>
>
>
>




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