[SI-LIST] Macromodeling, Reprise
- From: "Todd Westerhoff (twesterh)" <twesterh@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 28 Mar 2005 15:07:12 -0500
All,
There was a point in my previous posting that I'd still like to underscore.
It goes to the idea of IBIS defining both syntax and structure, and how we
might be able to move IBIS faster, to Chris' point.
Because IBIS defines the interconnect structure for the model, we need to
settle on new keywords and have tools updated to accommodate just about any
modeling change. By contrast, SPICE (or AMS, if you will) makes it possible
to model new things using existing syntax and tools. That's a big, big
deal.
My point - and I believe Donald's point as well - an IBIS macromodeling
syntax lets us respond to modeling changes without updating the language and
tools for each new requirement that comes along. Kumar predicted many years
ago that without a structural modeling syntax, IBIS would become overwhelmed
with syntax. In my opinion, this is exactly was has happened. That was the
original basis for my claim "Kumar was right" a number of years ago.
... And for those of you who don't have your Kumar memorabilia yet, it's
still available:
http://www.cafepress.com/kumar_right
AMS may well be the future, but we have an existing solution in front of us
with IBIS. Let's face it, IBIS has a hard time keeping pace with
semiconductor development ... so I'd like to see IBIS have the same
structural modeling advantage SPICE has. Give it a shot ... please. We are
so close already, and I really believe this one change will go a long way.
I see SSO as an additional issue for IBIS, on top of macromodeling.
Macromodeling gets you lots of capability whether buffer I/O currents are
predicted correctly or not. Add a buffer element with the right supply
currents and I/O modulation (thru BIRDs 95 and 97, or any other way) ... and
you can begin considering SSO.
As far as AMS goes, I guess the advantage is based on the skill of the model
developer. If the developer is skilled enough, I'm sure you could develop a
model that would correlate almost completely to its hardware counterpart.
This may well be the future - I'd just like to have a number of working,
practical examples before we go about declaring our Vision is now a Reality.
As far as HSpice goes, I hope we all realize that HSpice models are
generally just ported models anyway. The real models - the ones that get
correlated to silicon - live in CSE, ASX, TISpice or what have you. The
Hspice models we rave about are really ported and correlated versions of
those models. I'm not saying HSpice models aren't the best data we have -
they usually are - I'm just saying they're not sacrosanct.
As far as whether or not IBIS models everything HSpice does - I don't expect
it to. As long as I know what IBIS models do well, I can apply them
appropriately. If I know enough not to use a 100 MHz scope to measure to
measure a 500 ps rising edge, I think I can figure out where and when I can
benefit from an IBIS model. In that respect I agree with Chris - give the
users both HSpice and IBIS models and let them pick.
... But I still think we will all benefit from an IBIS structural modeling
language.
Todd.
Todd Westerhoff
High Speed Design Group Manager
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"Always do right.
This will gratify some people and astonish the rest."
- Mark Twain
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