[SI-LIST] Re: Macromodeling

Arpad, and Everyone else,

I have followed this discussion, or perhaps these
discussions with a lot of interest.  For the most
part I think that using the keywords seems like a
good idea.  While I do quite a lot of other stuff
besides SI analysis, I do have the occasion, quite
often, to use these tools.  If good models are
available from the manufacturer things work really
well.  Being able to add the ability to analyze
the effects of SSO on a small portion of a chip
would be great.  Being able to do this sort of
analysis on a whole board or system would be
really good too.

Often we attempt to run a full board crosstalk
simulation.  On several boards, where we have
used off-the-shelf ICs and FPGAs, we got really
good results and were able to avoid problems.

Some of our boards have mixed signal ASICs and
it would seem the the vendor, at least the ASIC
side of the house, does not feel that creating
an IBIS model is worth while.  Being that I have
other responsibilities and never could quite get
a handle on s2ibis2, I have used HSPICE a lot to
analyze portions of some ASIC boards.  Usually I
can find an interface from some other IBIS file
that gives me a similar waveform so I can crib
that info and use it.  I am reasonably sure that
the ASIC vendor will not be creating an *-AMS,
so we will probably be in the same place with
them.

I started out in hardware design some time ago.
Simulation seemed to spring from the synthesis
tools there.  As the level of abstraction for
synthesis got greater, the availability of
simulation  packages also got greater.  Anyone
working on a real analog synthesis package yet?

dav0



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