[SI-LIST] Long T reflection problems
- From: "Stein, James F (UK)" <james.stein@xxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 02 Mar 2005 14:59:33 +0000
Hi Everyone,
I have question about signal reflections, I have added some specific data=
but rule of thumb answers are all welcome as
i'm new to SI!
I have a bi-directional signal that is loaded with an LV-CMOS transceiver=
at 5pF on each end and a dt_r/dt/f of approx.
0.3 to 0.5 ns. The frequency of data across this is about 2 MHz. The=
distance between the two buffers is about 15mm.=0D
This signal needs to be observed externally with a logic analyser for test=
purposes.=0D
The track between the two transceivers is t'd to a test connector giving a=
t'd track length of about 150mm.=0D
In normal operation the analyser would not be connected so the long track=
section is o/c; when connected to an
analyser then you could probably add a metre to the total track length.
In this case, what sort of SI problems would I expect to see, both with the=
track o/c and also plugged into an analyser?
Would series termination be sufficient to prevent reflections, or should=
the test signal go through a buffer (last resort really) before
the test connector?
Regards
James
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