[SI-LIST] Re: Logic Family with ensured low outputs when no power isthere

I don't know of such a family (I have looked!), and I know of only a few 
specialized circumstances where such
"Known Good" output while the power is bad is really required.  In fact, 
many power monitor circuits themselves
do not comply with this requirement.  Usually, they begin to have 
defined output at very low values
of VDD (less than 1 volt).  An equally hard aspect of this problem is 
the response of the loads to the Reset input
when their Vdd is out of spec.  It does little good to guarantee the 
control signal to be "good" if the response of the controlled devices 
are uncertain.  Some tri-state buffers of the 244 type would glitch on a 
power ramp even if the
enable was pulled to VDD.  Sorry, I don't remember the particular 
family/families which displayed this behavior.

Once upon a time I crafted  a Power Reset circuit with guaranteed output 
over the range of  
0-5.5 volts.  It was built around an N-channel depletion mode JFET and 
some supporting circuitry to insure that
the power monitor output stays low impedance to ground until the power 
is really good.

In essence, there are two current sink switches in parallel to ground. 
The idea is that one circuit has
good performance while the power is unknown, but only crude threshold 
discrimination capability
(the JFET, which is ON with zero bias). The other circuit (the power 
monitor) has good threshold
discrimination  capabilities with uncertain performance with out-of-spec 
VDD.

If you really need to do it, it can be done.  I suggest that you 
thoroughly study the need for such a
circuit before embarking on implementing it, since it isn't an easy 
thing to get right.

As Dr. Laura says, "Now, go do the right thing."

Regards

Mike



Harjeet Singh Randhawa wrote:

>Hello All,
>I need a buffer for my power monitor reset output since it goes to 6-7
>loads. Normal logic families cannot be used because of unknown output
>states during when power is not there or has not reached a minimum
>threshold value.
>So I need a buffer which ensures low output in such condition. Can
>anyone recommend which digital logic family has such characteristic.
> 
>Thanx in advance,
>Harjeet.
> 
> 
>
>
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