[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight?

Hi Brian,

I am working on a DDR2 design and picked up on your comments below. What
are you specing for DDR2 chip to chip trace length matching?

Regards,
Shawn Arnold
High-Speed-Solutions and Design

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Moran, Brian P
Sent: Thursday, September 29, 2005 6:11 PM
To: dp@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Length matching of DDR-1 data lines - does it
really have to be that tight?


Dimiter,

Its been a long time since I've looked at DDR1.  I can't speak for all
cases but it is sometimes the case where a guideline will be written
based on what the authors feel are reasonable expectations of a good
physical design effort.=20 Someone might write +/- 50mil because they
feel this is a reasonable spec to hit and want to maximize timing
margins.  It doesn't necessarily mean that at +/- 100mils he design is
broken.  Its more a matter of trying to find the sweet spot between
optimized margins and routability.=20

Its been my experience that hitting +/-50mils is not unreasonable across
a byte lane.  We spec much tighter than that for DDR2, and want to
capture every ps of margin we can.  However, in the case you describe if
you do the math you'll see that the timing delta is extremely small
compared to DDR1 timing windows. So you make the call.=20




Brian P. Moran =20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Dimiter Popoff
Sent: Thursday, September 29, 2005 5:04 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Length matching of DDR-1 data lines - does it really
have to be that tight?

Hi everyone,
I found a number of appnotes on DDR-1 which state that data signals (and
the related, dqs and
dqm) must be length matched within +/- 50 mils. Now I read the spec of a
DDR chip I would use, and it says something like 0.4-0.5 nS max. skew
between these signals. At, say, 160 pS/inch, 50 mils means 8 pS .... Am
I overlooking something or are those recommendations I found just
nonsense? (I am talking the slowest, 133 MHz clock DDR, with up to 200
MHz in mind but unnecessary for this particular design).

Thanks,

Dimiter


------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------

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