[SI-LIST] Re: Length matching of DDR-1 data lines - does it really have to be that tight?

Matching the lengths of the data lines within +/- 50
mils would add unnecessary work for the PCB designer.
In my opinion, +/- 100 mil would be enough.
/dan



--- Dimiter Popoff <dp@xxxxxxxxxxx> wrote:

> Hi everyone,
> I found a number of appnotes on DDR-1 which state
> that data signals (and the related, dqs and
> dqm) must be length matched within +/- 50 mils. Now
> I read the spec of a DDR chip I would
> use, and it says something like 0.4-0.5 nS max. skew
> between these signals. At, say, 160 pS/inch,
> 50 mils means 8 pS .... Am I overlooking something
> or are those recommendations I found
> just nonsense? (I am talking the slowest, 133 MHz
> clock DDR, with up to 200 MHz in
> mind but unnecessary for this particular design).
> 
> Thanks,
> 
> Dimiter
> 
> 
>
------------------------------------------------------
> Dimiter Popoff               Transgalactic
> Instruments
> 
> http://www.tgi-sci.com
>
------------------------------------------------------
> 
>
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