[SI-LIST] Re: Leaving, then re-entering a reference plane

Don,
   My first, second, and third reactions to this are "AIIIIH!"
   Every time you cross the split, there is a remarkable impedance 
change, (reflection with a capitol R), and signal is induced into the 
second plane. IF you are very lucky, the stray signal won't encounter a 
resonance. IF! I am usually not that lucky. And when I am, some darn 
fool attaches something that makes it resonant. Since several of your 
signals cross the same gap, they will get a chance to shake hands with 
each other and swap bits. Cross talk! (Had to look close, thought for a 
moment I wrote Gross talk, which also applies.)
   You have your nice little transmission lines over a ground plane, and 
a virtual conductor on the other side of the plane. Life is good. Then 
you route the other conductor way off around the barn. And the other 
signals on your bus are similarly misrouted. You have in effect, twisted 
pairs that are untwisted, spread apart, and stacked on the other pairs 
in the bus. Lots of cross talk! Reflections on one signal are coupled to 
the others.
   If you split a plane, route signals over one plane or the other, but 
don't cross the gap!!! Don't even run along the edge! Stay a conductor 
width or a dielectric thickness (whichever is greater) away from that 
edge.
   So, crossing the split will cause Reflections, Cross talk, and 
Radiation. Anything that is radiating can also receive other radiation 
in the area. So your circuit will emit, and will be susceptible. 
Arrrgh!
   The best way to avoid EMI problems is signal integrity. You have a 
signal and its virtual return on back of the ground. Keep that signal a 
closely held secret. Treat each signal line as a transmission line, and 
keep the ground distance constant. Take your prototype into the EMI test 
area and look at the spectrum analyzer. Attempt to identify the spectral 
lines to figure out who is talking. Then look for trouble on that line.
   Good Hunting!
   Bill Grenoble

On Wed, 1 Jul 2009, Don Nelson wrote:

> Date: Wed, 01 Jul 2009 10:09:54 -0400
> From: Don Nelson <dhwn@xxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Leaving, then re-entering a reference plane
> 
> Hello,
>
>  I have a question about the effects of a split reference plane on a signal 
> that starts and ends referenced to the same plane, but encounters a second 
> plane along the way.  Here's a shot of what I'm talking about:
>
> http://idisk.me.com/dhwn/Public/split_plane.png
>
> All of those signals are part of a source-terminated QDRII (200 MHz) data 
> bus.  In this part of the stackup, the signals are on one layer of a 
> dual-stripline.  The other plane forming the stripline is a solid ground, and 
> there is no solid ground plane adjacent to the split power plane shown.  
> There are no capacitors between the two shown power planes.  (yes, lots of 
> things wrong there!  :-)
>
> Leaving aside the lesser effect of the more distant solid ground plane in the 
> dual-stripline, what happens to the return currents for these signals?  I 
> assume that the majority of the current flows on Plane 1 around the split 
> back to the drivers as shown, but the presence of the signal over Plane 2 
> must certainly induce a current there, and that's injecting energy into a 
> place that is not intended.  Plane 2 is well decoupled in that vicinity (you 
> can see vias attached to the plane there--these are decoupling caps) so I'd 
> like to think that at least medium frequency energy has a path to the gnd 
> plane (and back to the driver, if a bit circuitously), but what of the higher 
> frequency energy for which that path is too inductive?  I'm still a little 
> new at this and I'm having trouble "being the signal", as Eric Bogatin might 
> say.  :-)
>
> As for crosstalk, these signals are all members of the same bus (clock not 
> included), and there is a relatively large timing margin to work with.  My 
> working assumption is that the majority of the return current will flow 
> around the split on Plane 1, so these signals will all inductively 
> couple--but since they are all members of the same bus and since there is 
> large margin, I'm only moderately concerned by the edge distortion that will 
> occur as a result.  The only issue is that I'm a little fuzzy on how to 
> *quantify* the amount of distortion to be sure that it doesn't totally eat up 
> the rest of the margin--I don't have a simulator that can deal with return 
> paths and am still too much of a newbie to find a back-o-the-envelope 
> estimate.  I am also making the assumption that the impedance discontinuity 
> over each void is small compared with the edges of the signal.
>
> EMI?  I'm not even sure where to begin predicting that!  (that split plane is 
> layer 2, and layer 1 is a surface microstrip... I've got a bad feeling about 
> this!)
>
> Thanks in advance to everyone who helps shed some light on this,
>
> Kind regards,
> Don Nelson
> Netronome Systems
>
> --
> Don Nelson
>
> "The whole problem with the world is that fools and fanatics are so sure of 
> themselves, and wiser people so full of doubt" --Bertrand Russell
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