[SI-LIST] Re: Leaving, then re-entering a reference plane

Don

Unfortunately, you have a classical non-localizable split plane problem 
that is not possible to understand with intuition alone.  By 
non-localizable, I mean that the EM fields are not confined to a small 
region that can be easily analyzed.  Non-localizable problems occur when 
there are plane excitations due to vias penetrating planes, or traces 
crossing plane splits.  At the discontinuities, the signals will inject 
a parallel plate mode wave into the split core power plane, which will 
cause excitation at the 1st, 3rd and 5th harmonics of the incident bit 
pattern.  When the pattern spectrum (and it's harmonics) aligns with a 
power plane resonance, a standing wave pattern will develop that will 
increase the power system noise, along with the signaling noise, jitter 
and crosstalk. 

What you will need to look for is the parallel resonant frequency of the 
power plane, that is, the resonant frequency of the bypass capacitor 
mounting inductance, and the plane capacitance.  However, since there is 
no ground plane adjacent to the split power plane, the impedance will 
most likely be high on the average, and exceedingly high at resonance.  
This has the potential of being a very bad thing, and extremely 
sensitive to process variations of the PCB and the capacitors being used. 

You have 3 possible courses of action, in order of best to worst.

1) Redesign to remove the split.
2) Simulate it in a planar fullwave solver like Ansoft SIWave.
3) Build it and measure the signal and power system.  A spectrum 
analyzer would be very useful to determine where the resonant peaks 
occur, and whether they will cause meaningful noise, crosstalk, or jitter.


regards,

Scott

-- 
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC


Don Nelson wrote:
> Hello,
>
>   I have a question about the effects of a split reference plane on a signal 
> that starts and ends referenced to the same plane, but encounters a second 
> plane along the way.  Here's a shot of what I'm talking about:
>
> http://idisk.me.com/dhwn/Public/split_plane.png
>
> All of those signals are part of a source-terminated QDRII (200 MHz) data 
> bus.  In this part of the stackup, the signals are on one layer of a 
> dual-stripline.  The other plane forming the stripline is a solid ground, and 
> there is no solid ground plane adjacent to the split power plane shown.  
> There are no capacitors between the two shown power planes.  (yes, lots of 
> things wrong there!  :-)
>
> Leaving aside the lesser effect of the more distant solid ground plane in the 
> dual-stripline, what happens to the return currents for these signals?  I 
> assume that the majority of the current flows on Plane 1 around the split 
> back to the drivers as shown, but the presence of the signal over Plane 2 
> must certainly induce a current there, and that's injecting energy into a 
> place that is not intended.  Plane 2 is well decoupled in that vicinity (you 
> can see vias attached to the plane there--these are decoupling caps) so I'd 
> like to think that at least medium frequency energy has a path to the gnd 
> plane (and back to the driver, if a bit circuitously), but what of the higher 
> frequency energy for which that path is too inductive?  I'm still a little 
> new at this and I'm having trouble "being the signal", as Eric Bogatin might 
> say.  :-)
>
> As for crosstalk, these signals are all members of the same bus (clock not 
> included), and there is a relatively large timing margin to work with.  My 
> working assumption is that the majority of the return current will flow 
> around the split on Plane 1, so these signals will all inductively 
> couple--but since they are all members of the same bus and since there is 
> large margin, I'm only moderately concerned by the edge distortion that will 
> occur as a result.  The only issue is that I'm a little fuzzy on how to 
> *quantify* the amount of distortion to be sure that it doesn't totally eat up 
> the rest of the margin--I don't have a simulator that can deal with return 
> paths and am still too much of a newbie to find a back-o-the-envelope 
> estimate.  I am also making the assumption that the impedance discontinuity 
> over each void is small compared with the edges of the signal.  
>
> EMI?  I'm not even sure where to begin predicting that!  (that split plane is 
> layer 2, and layer 1 is a surface microstrip... I've got a bad feeling about 
> this!)
>
> Thanks in advance to everyone who helps shed some light on this,
>
> Kind regards,
> Don Nelson
> Netronome Systems
>    
> --
> Don Nelson
>
> "The whole problem with the world is that fools and fanatics are so sure of 
> themselves, and wiser people so full of doubt" --Bertrand Russell
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-- 
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC

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